Intel Agilex® 7 Variable Precision DSP Blocks User Guide

ID 683037
Date 4/11/2023
Public

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10.3.2. Registers Tab

Table 109.  Registers Tab
Parameter IP Generated Parameter Value Default Value Description
Clear Signal Setting
Type of clear signal clear_type

none

aclr

sclr

none

Specify the clear signal behavior for all registers in the floating-point DSP block.

  • none: Select to not use any clear signal.
  • aclr: Select to use asynchronous clear signal type for all registers.
  • sclr: Select to use synchronous clear signal type for all registers.
Enable clr0 signal for all input registers enable_clr0

No

Yes

No Select Yes to enable clr[0] signal for all input registers.
Enable clr1 for output and pipeline registers enable_clr1

No

Yes

No Select Yes to enable clr[1] signal for output and pipeline registers.
Input Registers
Enable for input 'accumulate' accumulate_clken

no_reg

ena0

ena1

ena2

no_reg

Specify the clock enable signal for accumulate input register.

Select no_reg to disable the register.

Enable for input 'fp32_adder_a' fp32_adder_a_clken

no_reg

ena0

ena1

ena2

ena0

Specify the clock enable signal for fp32_adder_a input register.

Select no_reg to disable the register.

Enable for input 'fp32_adder_b' fp32_adder_b_clken

no_reg

ena0

ena1

ena2

no_reg

Specify the clock enable signal for fp32_adder_b input register.

Select no_reg to disable the register.

Enable for input 'fp32_mult_a' fp32_mult_a_clken

no_reg

ena0

ena1

ena2

ena0

Specify the clock enable signal for fp32_mult_a input register.

Select no_reg to disable the register.

Enable for input 'fp32_mult_b' fp32_mult_b_clken

no_reg

ena0

ena1

ena2

ena0

Specify the clock enable signal for fp32_mult_b input register.

Select no_reg to disable the register.

Enable for input 'fp16_mult_input' fp16_mult_input_clken

no_reg

ena0

ena1

ena2

no_reg

Specify the clock enable signal for fp16_mult_input input register.

Select no_reg to disable the register.

Output Registers
Enable output register output_clken

no_reg

ena0

ena1

ena2

ena0

Specify the clock enable signal for output register.

Select no_reg to disable the register.

Pipeline Registers
Enable 'accum_adder' register accum_adder_clken

no_reg

ena0

ena1

ena2

no_reg

Specify the clock enable signal for accum_adder pipeline register.

Select no_reg to disable the register.

Enable 'adder_input' register adder_input_clken

no_reg

ena0

ena1

ena2

ena0

Specify the clock enable signal for adder_input pipeline register.

Select no_reg to disable the register.

Enable 'adder_pl' register adder_pl_clken

no_reg

ena0

ena1

ena2

no_reg

Specify the clock enable signal for adder_pl pipeline register.

Select no_reg to disable the register.

Enable 'fp32_adder_a_chainin_pl' register fp32_adder_a_chainin_pl_clken

no_reg

ena0

ena1

ena2

ena0

Specify the clock enable signal for fp32_adder_a_chainin_pl pipeline register.

Select no_reg to disable the register.

Enable 'accum_pipeline' register accum_pipeline_clken

no_reg

ena0

ena1

ena2

no_reg

Specify the clock enable signal for accum_pipeline register.

Select no_reg to disable the register.

Enable 'mult_pipeline' register mult_pipeline_clken

no_reg

ena0

ena1

ena2

ena0

Specify the clock enable signal for mult_pipeline register.

Select no_reg to disable the register.

Enable 'fp32_adder_a_chainin_2nd_pl' register fp32_adder_a_chainin_2nd_pl_clken

no_reg

ena0

ena1

ena2

ena0

Specify the clock enable signal for fp32_adder_a_chainin_2nd_pl pipeline register.

Select no_reg to disable the register.

Enable 'accum_2nd_pipeline' register accum_2nd_pipeline_clken

no_reg

ena0

ena1

ena2

no_reg

Specify the clock enable signal for accum_2nd_pipeline register.

Select no_reg to disable the register.

Enable 'mult_2nd_pipeline' register mult_2nd_pipeline_clken

no_reg

ena0

ena1

ena2

ena0

Specify the clock enable signal for mult_2nd_pipeline register.

Select no_reg to disable the register.