Intel Agilex® 7 Variable Precision DSP Blocks User Guide

ID 683037
Date 4/11/2023

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2.1.8. Systolic Register for Fixed-point Arithmetic

There are two sets of systolic registers per variable precision DSP block and each set supports up to 44 bits chain in and chain out adder. If the variable precision DSP block is not configured in fixed-point arithmetic systolic FIR mode, both sets of systolic registers are bypassed.

The first set of systolic registers consists of 18-bit and 19-bit registers that are used to register the 18-bit and 19-bit inputs of the upper multiplier, respectively.

The second set of systolic registers are used to delay the chainin input from the previous variable precision DSP block.

Below are the guidelines when implementing systolic registers in your design:
  • The output register must be enabled when using systolic registers.
  • First and second pipeline registers are optional when using systolic registers. If second pipeline is enabled, use the same clock enable as the input systolic register.
  • The chainin systolic register always has the same clock enable as the output register.