Intel Agilex® 7 Variable Precision DSP Blocks User Guide

ID 683037
Date 4/11/2023
Public

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4.1.1.1. Restrictions for Input Registers

The following are the clock enable restrictions for input registers:
  • When using 9 x 9 sum of 4 operational mode, the following input signal pairs must use the same clock enable settings:
    • ax and bx
    • ay and by
    • cx and dx
    • cy and dy
  • If the input registers for SUB, NEGATE, ACCUMULATE, and LOADCONST signals are enabled, these registers must use the same clock enable settings.
  • Disable the input registers for SUB, NEGATE, ACCUMULATE, and LOADCONST signals if these signals are driven by a constant value.