Intel Agilex® 7 Variable Precision DSP Blocks User Guide

ID 683037
Date 4/11/2023
Public

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4.2.1.1. FP32 Operation Modes Supported Register Configurations

Table 26.  Supported Register Configurations For FP32 Multiplication Mode
Latency Input Register Pipeline Register Output Register
fp32_mult_a_clken fp32_mult_b_clken mult_pipeline_clken mult_2nd_pipeline_clken output_clken
0 Disable Disable Disable Disable Disable
1 Enable Enable Disable Disable Disable
1 Disable Disable Disable Disable Enable
2 Enable Enable Disable Enable Enable
≥3 Disable Enable Disable, enable Enable Enable
Table 27.  Supported Register Configurations For FP32 Addition or Subtraction Mode
Latency Data Input Register Pipeline Register Adder Input Register Output Register
fp32_adder_a_clken fp32_adder_b_clken fp32_adder_a_chainin_pl_clken fp32_adder_a_chainin_2nd_pl_clken adder_input_clken output_clken
0 Disable Disable Disable Disable Disable Disable
1 Enable Enable Disable Disable Disable Disable
1 Disable Disable Disable Disable Disable Enable
2 Enable Enable Disable Disable Disable Enable
≥3 Enable Enable Disable, enable Disable, enable Enable Enable
Table 28.  Supported Register Configurations For FP32 Multiplication with Addition or Subtraction Mode
Latency Data Input Register Adder 1st Pipeline Register Adder 2nd Pipeline Register Multiplier 1st Pipeline Register Multiplier 2nd Pipeline Register Adder Input Register Output Register
fp32_adder_a_clken fp32_mult_a_clken fp32_mult_b_clken fp32_adder_a_chainin_pl_clken fp32_adder_a_chainin_2nd_pl_clken mult_pipeline_clken mult_2nd_pipeline_clken adder_input_clken output_clken
0 Disable Disable Disable Disable Disable Disable Disable Disable Disable
1 Enable Enable Enable Disable Disable Disable Disable Disable Disable
1 Disable Disable Disable Disable Disable Disable Disable Disable Enable
2 Enable Enable Enable Disable Disable Disable Disable Disable Enable
≥3 Enable Enable Enable Disable, enable Disable, enable Disable Disable Enable Enable
≥4 Enable Enable Enable Disable, enable Disable, enable Disable, enable Enable Enable Enable
Table 29.  Supported Register Configurations For FP32 Multiplication with Accumulation Mode
Latency Data Input Register Adder 1st Pipeline Register Adder 2nd Pipeline Register Multiplier 1st Pipeline Register Multiplier 2nd Pipeline Register Adder Input Register Output Register
accumulate_clken fp32_mult_a_clken fp32_mult_b_clken accum_pipeline_clken accum_2nd_pipeline_clken mult_pipeline_clken mult_2nd_pipeline_clken accum_adder_clken adder_input_clken output_clken
1 Disable Disable Disable Disable Disable Disable Disable Disable Disable Enable
2 Enable Enable Enable Disable Disable Disable Disable Disable Disable Enable
≥3 Enable Enable Enable Disable, enable Disable, enable Disable Disable Enable Enable Enable
≥4 Enable Enable Enable Disable, enable Disable, enable Disable, enable Enable Enable Enable Enable
Table 30.  Supported Register Configurations For FP32 Vector One Mode
Latency Data Input Register Adder 1st Pipeline Register Adder 2nd Pipeline Register Multiplier 1st Pipeline Register Multiplier 2nd Pipeline Register Adder Input Register Output Register
fp32_adder_a_clken fp32_mult_a_clken fp32_mult_b_clken fp32_adder_a_chainin_pl_clken fp32_adder_a_chainin_pl_clken mult_pipeline_clken mult_2nd_pipeline_clken adder_input_clken output_clken
0 Disable Disable Disable Disable Disable Disable Disable Disable Disable
1 Enable Enable Enable Disable Disable Disable Disable Disable Disable
1 Disable Disable Disable Disable Disable Disable Disable Disable Enable
2 Enable Enable Enable Disable Disable Disable Disable Disable Enable
≥3 Enable Enable Enable Disable, enable Disable, enable Disable Disable Enable Enable
≥4 Enable Enable Enable Disable, enable Disable, enable Disable, enable Enable Enable Enable
Table 31.  Supported Register Configurations For FP32 Vector Two Mode
Latency Data Input Register Adder 1st Pipeline Register Adder 2nd Pipeline Register Multiplier 1st Pipeline Register Multiplier 2nd Pipeline Register Adder Input Register Output Register
fp32_adder_a_clken fp32_mult_a_clken fp32_mult_b_clken fp32_adder_a_chainin_pl_clken fp32_adder_a_chainin_pl_clken mult_pipeline_clken mult_2nd_pipeline_clken adder_input_clken output_clken
0 Disable Disable Disable Disable Disable Disable Disable Disable Disable
1 Enable Enable Enable Disable Disable Disable Disable Disable Disable
1 Disable Disable Disable Disable Disable Disable Disable Disable Enable
2 Enable Enable Enable Disable Disable Disable Disable Disable Enable
≥3 Enable Enable Enable Disable, enable Disable, enable Disable, enable Enable Enable Enable