40G Ethernet MAC and PHY Intel® FPGA IP Core

The 40G Ethernet MAC and PHY Intel® FPGA IP core offers IEEE 802.3ba-2010. 40 Gbps Ethernet is an industry standard and is compliant for media access control (MAC) and PHY (PCS+PMA) functions. It enables an Intel® FPGA to interface to another device over a copper or optical transceiver module. The IP supports IEEE 1588 v2 standard with two-step timestamping as well as backplane capability on a variety of Intel® Stratix® or Intel® Arria® FPGAs.

Read the Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function user guide ›

Read the Low Latency E-Tile 40G Ethernet Intel® FPGA IP user guide ›

Read the Intel® Stratix® 10 Low Latency 40-Gbps Ethernet IP Core user guide ›

Read the Low Latency 40-Gbps Ethernet IP Core user guide ›

Read the 40-and 100-Gbps Ethernet MAC and PHY MegaCore Function user guide ›

Read the Intel® Stratix® 10 Low Latency 40G Ethernet Design Example user guide ›

Read the Low Latency 40G Ethernet Design Example user guide ›

40G Ethernet MAC and PHY Intel® FPGA IP Core

IP Quality Metrics

Basics

Low Latency

Year IP was first released

2011

2014

First version of Intel Quartus Prime Software supported

16.1

16.1

Ordering codes

IP-40GEMAC

IP-40GEPHY

IP-40GEMACPHY

IP-40BASEKR4PHY

IP-40GEUMACPHY: Low latency 40G Ethernet MAC & PHY

IP-40GEUMACPHYF: Low latency 40G Ethernet MAC & PHY with 1588

IP-40GBASEKR4PHY: Low latency 40G Ethernet MAC & 40GBASE-KRPHY with FEC

IP40GU: Low Latency 40-GE Intel Stratix 10 IP

IP-40GETILEMAC: Low Latency E-Tile 4-G Ethernet Intel FPGA IP

Status

Production

Production

Deliverables

Low Latency

Customer deliverables include the following:

Design file (encrypted source code or post-synthesis netlist)

Simulation model for ModelSim*- Intel FPGA Edition

Timing and/or layout constraints

Documentation with revision control

Readme file

Y

Y

Any additional customer deliverables provided with IP

 

 

Parameterization GUI allowing end user to configure IP

Y

Y

IP is enabled for Intel FPGA IP Evaluation Mode Support

Y

Y

Source language

Verilog

Verilog

Testbench language

 

 

Software drivers provided

N

N

Driver OS Support

 

 

Implementation

Low Latency

User interface

Avalon-ST (Datapath), Avalon-MM (Management)

Avalon-ST (Datapath), Avalon-MM (Management) 

IP-XACT metadata

N

N

Verification

Low Latency

Simulators supported

Mentor Graphics*, Synopsys*, Cadence*

Mentor Graphics*, Synopsys*, Cadence*

Hardware validated

Intel Arria 10

Intel Arria 10, Intel Stratix 10

Industry-standard compliance testing performed

N

N

If Yes, which test(s)?

 

 

If Yes, on which Intel FPGA device(s)?

 

 

If Yes, date performed

 

 

If No, is it planned?

N

Y

Interoperability

Low Latency

IP has undergone interoperability testing

N

Y

If yes, on which Intel FPGA device(s)

 

Intel Stratix 10 GX

Interoperability reports available

N

N