Intel® Stratix® 10 Low Latency 40G Ethernet Design Example User Guide

ID 683718
Date 1/27/2021
Public
Download

1. Quick Start Guide

Updated for:
Intel® Quartus® Prime Design Suite 20.3

The Intel® Stratix® 10 Low Latency (LL) 40G Ethernet IP core provides a simulation testbench and a hardware design example that supports compilation and hardware testing. When you generate the design example, the Intel® Quartus® Prime IP parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware.

In addition, you can download the compiled hardware design to the Intel device-specific development kit for interoperative testing. The also includes a compilation-only example project that you can use to quickly estimate IP core area and timing.

The Intel® Stratix® 10 Low Latency (LL) 40G Ethernet IP supports design example generation with a wide range of parameters. However, the design examples do not cover all possible parameterizations of the Intel Stratix 10 LL 40GbE IP Core.

Figure 1. Development Steps for the Design Example