A. Document Revision History for Intel® Stratix® 10 Low Latency 40G Ethernet Design Example User Guide
Document Version | Intel® Quartus® Prime Version | Changes |
---|---|---|
2021.01.27 | 20.3 |
|
2020.02.03 | 19.1 | Added support for VCS* MX and Xcelium* simulators. |
2019.05.15 | 19.1 | Changed word "lower" to "upper" in the Source address upper 16 bits register. |
2018.11.15 | 18.1 | Added the Packet Client registers in section: Intel® Stratix® 10 LL 40GbE Design Example Registers. |
2017.05.08 | 17.1 Intel® Stratix® 10 ES Editions | Initial release. |
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