Intel® Stratix® 10 Low Latency 40G Ethernet Design Example User Guide

ID 683718
Date 1/27/2021
Public

A. Document Revision History for Intel® Stratix® 10 Low Latency 40G Ethernet Design Example User Guide

Document Version Intel® Quartus® Prime Version Changes
2021.01.27 20.3
  • Revised the Directory Structure for the Generated Design Example figure.
    • Removed outdated .regmap file.
    • Updated compilation_test_design folder name.
  • Added new section: Ethernet Toolkit
  • Corrected minor errors and typos.
2020.02.03 19.1 Added support for VCS* MX and Xcelium* simulators.
2019.05.15 19.1 Changed word "lower" to "upper" in the Source address upper 16 bits register.
2018.11.15 18.1 Added the Packet Client registers in section: Intel® Stratix® 10 LL 40GbE Design Example Registers.
2017.05.08 17.1 Intel® Stratix® 10 ES Editions Initial release.