Intel® Stratix® 10 Low Latency 40G Ethernet Design Example User Guide

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ID 683718
Date 1/27/2021
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Ethernet Toolkit Overview 4. Intel® Stratix® 10 Low Latency 40GbE IP Core User Guide Archives A. Document Revision History for Intel® Stratix® 10 Low Latency 40G Ethernet Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Simulation Design Example Components 1.3. Hardware Design Example Components 1.4. Generating the Design Example 1.5. Simulating the Intel Stratix 10 LL 40GbE Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Intel Stratix 10 LL 40GbE Hardware Design Example
2. Design Example Description x
2.1. Design Example Behavior 2.2. Design Example Interface Signals 2.3. Intel Stratix 10 LL 40GbE Design Example Registers
3. Ethernet Toolkit Overview x
3.1. Features
1. Quick Start Guide
2. Design Example Description
3. Ethernet Toolkit Overview
4. Intel® Stratix® 10 Low Latency 40GbE IP Core User Guide Archives
A. Document Revision History for Intel® Stratix® 10 Low Latency 40G Ethernet Design Example User Guide

A. Document Revision History for Intel® Stratix® 10 Low Latency 40G Ethernet Design Example User Guide

Document Version Intel® Quartus® Prime Version Changes
2021.01.27 20.3
  • Revised the Directory Structure for the Generated Design Example figure.
    • Removed outdated .regmap file.
    • Updated compilation_test_design folder name.
  • Added new section: Ethernet Toolkit
  • Corrected minor errors and typos.
2020.02.03 19.1 Added support for VCS* MX and Xcelium* simulators.
2019.05.15 19.1 Changed word "lower" to "upper" in the Source address upper 16 bits register.
2018.11.15 18.1 Added the Packet Client registers in section: Intel® Stratix® 10 LL 40GbE Design Example Registers.
2017.05.08 17.1 Intel® Stratix® 10 ES Editions Initial release.
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