Intel® Stratix® 10 Low Latency 40G Ethernet Design Example User Guide

ID 683718
Date 1/27/2021

1.3. Hardware Design Example Components

Figure 4.  Intel Stratix 10 LL 40GbE Hardware Design Example High Level Block Diagram

The Intel Stratix 10 LL 40GbE hardware design example includes the following components:

  • Intel Stratix 10 LL 40GbE IP core.
  • Client logic that coordinates the programming of the IP core, and packet generation and checking.
  • ATX PLL to drive the device transceiver channel clocks.
  • IOPLL to generate a 100 MHz clock from a 50 MHz input clock to the hardware design example.
  • JTAG controller that communicates with the Intel® System Console. You communicate with the client logic through the System Console.
Table 2.   Intel Stratix 10 LL 40GbE IP Core Hardware Design Example File Descriptions

File Names


eth_ex_40 g.qpf Intel® Quartus® Prime project file.
eth_ex_40 g.qsf Intel® Quartus® Prime project settings file.
eth_ex_40 g.sdc Synopsys* Design Constraints file. You can copy and modify this file for your own Intel Stratix 10 LL 40GbE design.
eth_ex_40 g.v Top-level Verilog HDL design example file.
common/ Hardware design example support files.

Main file for accessing System Console.