Intel® Stratix® 10 Low Latency 40G Ethernet Design Example User Guide

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ID 683718
Date 1/27/2021
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Ethernet Toolkit Overview 4. Intel® Stratix® 10 Low Latency 40GbE IP Core User Guide Archives A. Document Revision History for Intel® Stratix® 10 Low Latency 40G Ethernet Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Simulation Design Example Components 1.3. Hardware Design Example Components 1.4. Generating the Design Example 1.5. Simulating the Intel Stratix 10 LL 40GbE Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Intel Stratix 10 LL 40GbE Hardware Design Example
2. Design Example Description x
2.1. Design Example Behavior 2.2. Design Example Interface Signals 2.3. Intel Stratix 10 LL 40GbE Design Example Registers
3. Ethernet Toolkit Overview x
3.1. Features
1. Quick Start Guide
2. Design Example Description
3. Ethernet Toolkit Overview
4. Intel® Stratix® 10 Low Latency 40GbE IP Core User Guide Archives
A. Document Revision History for Intel® Stratix® 10 Low Latency 40G Ethernet Design Example User Guide

1.3. Hardware Design Example Components

Figure 4.  Intel Stratix 10 LL 40GbE Hardware Design Example High Level Block Diagram

The Intel Stratix 10 LL 40GbE hardware design example includes the following components:

  • Intel Stratix 10 LL 40GbE IP core.
  • Client logic that coordinates the programming of the IP core, and packet generation and checking.
  • ATX PLL to drive the device transceiver channel clocks.
  • IOPLL to generate a 100 MHz clock from a 50 MHz input clock to the hardware design example.
  • JTAG controller that communicates with the Intel® System Console. You communicate with the client logic through the System Console.
Table 2.   Intel Stratix 10 LL 40GbE IP Core Hardware Design Example File Descriptions

File Names

Description

eth_ex_40 g.qpf Intel® Quartus® Prime project file.
eth_ex_40 g.qsf Intel® Quartus® Prime project settings file.
eth_ex_40 g.sdc Synopsys* Design Constraints file. You can copy and modify this file for your own Intel Stratix 10 LL 40GbE design.
eth_ex_40 g.v Top-level Verilog HDL design example file.
common/ Hardware design example support files.
hwtest/main.tcl

Main file for accessing System Console.
Level Two Title

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