2.2. Design Example Interface Signals
The Intel Stratix 10 LL 40GbE testbench is self-contained and does not require you to drive any input signals.
Drive at 50 MHz. The intent is to drive it from a 50 MHz oscillator on the board.
The hardware design example routes this clock to the input of an IOPLL on the device and configures the IOPLL to drive a 100 MHz clock internally.
|clk_ref||Input||Drive at 644.53125 MHz.|
|cpu_resetn||Input||Resets the IP core. Active low. Drives the global hard reset csr_reset_n to the IP core.|
|tx_serial[3:0]||Output||Transceiver PHY output serial data.|
|rx_serial[3:0]||Input||Transceiver PHY input serial data.|
|user_led[7:0]||Output||Status signals. The hardware design example connects these bits to drive LEDs on the target board. Individual bits reflect the following signal values and clock behavior:
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