Intel® Stratix® 10 Low Latency 40G Ethernet Design Example User Guide

ID 683718
Date 1/27/2021

1.7. Testing the Intel Stratix 10 LL 40GbE Hardware Design Example

After you compile the Intel Stratix 10 LL 40GbE core design example and configure it on your Intel® Stratix® 10 device, you can use the System Console to program the IP core and its embedded Native PHY IP core registers.

To turn on the System Console and test the hardware design example, follow these steps:

  1. After the hardware design example is configured on the Intel® Stratix® 10 device, in the Intel® Quartus® Prime Pro Edition software, on the Tools menu, click System Debugging Tools > System Console.
  2. In the Tcl Console pane, type cd hwtest to change directory to <design_example_dir>/hardware_test_design/hwtest.
  3. Type source main.tcl to open a connection to the JTAG master.

You can program the IP core with the following design example commands:

  • chkphy_status: Displays the clock frequencies and PHY lock status.
  • chkmac_stats: Displays the values in the MAC statistics counters.
  • clear_all_stats: Clears the IP core statistics counters.
  • start_pkt_gen: Starts the packet generator.
  • stop_pkt_gen: Stops the packet generator.
  • loop_on: Turns on internal serial loopback
  • loop_off: Turns off internal serial loopback.
  • reg_read <addr>: Returns the IP core register value at <addr>.
  • reg_write <addr> <data>: Writes <data> to the IP core register at address <addr>.