Intel® Stratix® 10 Low Latency 40G Ethernet Design Example User Guide

ID 683718
Date 1/27/2021

1.1. Directory Structure

The Intel Stratix 10 LL 40GbE IP core design example file directories contain the following generated files for the design example.

Figure 2. Directory Structure for the Generated Design Example
  • The simulation files (testbench for simulation only) are located in <design_example_dir>/example_testbench.
  • The compilation-only example design is located in <design_example_dir>/compilation_test_design.
  • The hardware configuration and test files (the hardware design example) are located in <design_example_dir>/hardware_test_design.