Intel® Stratix® 10 Low Latency 40G Ethernet Design Example User Guide

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ID 683718
Date 1/27/2021
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Ethernet Toolkit Overview 4. Intel® Stratix® 10 Low Latency 40GbE IP Core User Guide Archives A. Document Revision History for Intel® Stratix® 10 Low Latency 40G Ethernet Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Simulation Design Example Components 1.3. Hardware Design Example Components 1.4. Generating the Design Example 1.5. Simulating the Intel Stratix 10 LL 40GbE Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Intel Stratix 10 LL 40GbE Hardware Design Example
2. Design Example Description x
2.1. Design Example Behavior 2.2. Design Example Interface Signals 2.3. Intel Stratix 10 LL 40GbE Design Example Registers
3. Ethernet Toolkit Overview x
3.1. Features
1. Quick Start Guide
2. Design Example Description
3. Ethernet Toolkit Overview
4. Intel® Stratix® 10 Low Latency 40GbE IP Core User Guide Archives
A. Document Revision History for Intel® Stratix® 10 Low Latency 40G Ethernet Design Example User Guide

1.2. Simulation Design Example Components

Figure 3.  Intel Stratix 10 LL 40GbE Design Example Block Diagram

The simulation design example top-level test file is basic_avl_tb_top.sv. This file instantiates and connects an ATX PLL. It includes a task to send and receive 10 packets. The simulation design example for 40GBASE-KR4 variations also exercises auto-negotiation and link training, if enabled.

Table 1.   Intel Stratix 10 LL 40GbE IP Core Testbench File Descriptions

File Names

Description

Testbench and Simulation Files
basic_avl_tb_top.sv Top-level testbench file. The testbench instantiates the DUT and runs Verilog HDL tasks to generate and accept packets. The testbench also implements auto-negotiation and link training if enabled in a 40GBASE-KR4/CR4 DUT.
Testbench Scripts
run_vsim.do

The Mentor Graphics* ModelSim* script to run the testbench.

run_vcs.sh

The Synopsys* VCS* script to run the testbench.

run_vcsmx.sh

The Synopsys* VCS* MX script (combined Verilog HDL and System Verilog with VHDL) to run the testbench.

run_ncsim.sh

The Cadence NCSim script to run the testbench.

run_xcelium.sh The Cadence Xcelium* script to run the testbench.
Level Two Title