Stratix® V GX 100G Development Kit
100G Development Kit, Stratix® V GX Edition enables a thorough evaluation of 100G designs.
100G Development Kit, Stratix® V GX Edition enables a thorough evaluation of 100G designs by allowing you to:
- Support 10G/40G and 100G line interfaces through optical modules.
- Support applications requiring external memory interfaces, through 6x32-bit DDR3 and 1x36- and 1x18-bit QDRII BL2 memory banks.
- Use system-side interfaces via two pairs of FCI AirMax connectors
- Complete line-side (optical modules) to system-side (AirMax connector) datapath analysis.
- Evaluate transceiver performance up to 12.5 Gbps.
- Verify physical medium attachment (PMA) compliance to 10G/40G/100G Ethernet, Interlaken, CEI-6G/11G, and other major standards.
- Validate interoperability between optical modules, such as SFP, SFP+, QSFP, and CFP.
Table 1. 100G Development Kit, Stratix® V GX Edition Ordering Information
| Ordering Code | Price | Ordering Information |
|---|---|---|
| DK-100G-5SGXEA7N | $24,995 |
In North America, call 1-888-800-0631 or contact your local distributor. For International sales, contact your local distributor. |
Note:
Buyer represents that it is a product developer, software developer or system integrator and acknowledges that this product is an evaluation kit that is not FCC authorized, is made available solely for evaluation and software development, and may not be resold.
Development Kit Contents
The 100G Development Kit, Stratix® V GX Edition has the following features:
- Stratix® V GX development board
- Featured device: 5SGXEA7N2F45C2N
- EPM2210F324C3N, MAX® II 324-pin CPLD
- FPGA configuration
- Fast Passive Parallel (FPP) configuration
- 1-Gb flash storage for two configuration images (factory and user)
- On-board USB-Blaster™ II cable for use with the Intel® Quartus® Prime Programmer, Nios® II software and System Console
- JTAG header for external USB-Blaster cable
- Memory
- Twelve 2-Gb DDR3 SDRAM
- Two 72-Mb QDR II SRAM
- General user input/output
- Four user push buttons
- Two DIP switches
- Eight user LEDs
- Two-line character LCD
- Ten configuration status LEDs
- Components and interfaces
- 10/100/1000 Ethernet PHY and RJ-45 jack
- 48 transceiver channels
- Two channels for SMA interface
- Four channels for SFP+ interface
- Eight channels for QSFP interface
- 10 channels for CFP interface
- 24 channels for Interlaken interface
- Temperature measurement circuitry
- Die temperature
- Power
- 19-V DC input
- 2.5-mm barrel jack for DC power input
- On/off power slide switch
- On-board power measurement circuitry
- Intel® Quartus® Prime design software, Development Kit Edition (DKE)
- License to use full version of Intel® Quartus® Prime design software for one year.
Table 2. Collateral for the 100G Development Kit, Stratix® V GX Edition
Document |
Description |
Version |
|---|---|---|
Information about setting up the 100G Development Kit and using the included software. |
11.1 |
|
Detailed information about board components and interfaces. |
11.1 |
|
Kit Installation › (For boards with ES Silicon) |
Full installation of all files included in the development kit, including the reference manual, user guide, quick-start guide, BOM, layout, PCB, schematics, Board Update Portal example file, and so on. |
11.1 |
Full installation of all files included in the development kit, including the reference manual, user guide, quick-start guide, BOM, layout, PCB, schematics, Board Update Portal example file, and so on. |
12 |
Additional Resources
Design Store
Intel® FPGA design examples provide efficient solutions for common design challenges. Visit the Design Store for Intel® FPGAs and RocketBoards.org to learn more.
Support Community
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