Low Latency 40-Gbps Ethernet Intel® Stratix® 10 IP Core User Guide

ID 683600
Date 10/12/2021
Public
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Document Table of Contents

1. Datasheet

Updated for:
Intel® Quartus® Prime Design Suite 21.3
IP Version 19.1.0

The Intel® Stratix® 10 Low Latency 40-Gbps Ethernet (LL 40GbE) IP core implements the IEEE 802.3-2010 40G Ethernet Standard. The IP core includes options to support unidirectional transport as defined in Clause 66 of the IEEE 802.3-2012 Ethernet Standard and to support the IEEE 802.3-2012 Backplane Ethernet Standard.

The MAC client side interface for the Intel Stratix 10 LL 40GbE IP core is a 128-bit Avalon® streaming interface (Avalon-ST).

The IP core provides standard media access control (MAC), physical coding sublayer (PCS), and physical medium attachment (PMA) functions. The PHY comprises the PCS and PMA.

Figure 1.  Intel Stratix 10 LL 40GbE Block DiagramMain blocks, internal connections, and external block requirements.