Low Latency 40-Gbps Ethernet Intel® Stratix® 10 IP Core User Guide

ID 683600
Date 6/20/2023
Public
Document Table of Contents

3.7. Compiling the Full Design and Programming the FPGA

You can use the Start Compilation command on the Processing menu in the Intel® Quartus® Prime software to compile your design. After successfully compiling your design, program the targeted Intel® FPGA with the Programmer and verify the design in hardware.

Note: The Intel Stratix 10 LL 40GbE core design example synthesis directories include Synopsys Constraint (.sdc) files that you can copy and modify for your own design.