Low Latency 40-Gbps Ethernet Intel® Stratix® 10 IP Core User Guide

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ID 683600
Date 6/20/2023
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Document Table of Contents
Document Table of Contents x
1. Datasheet 2. Intel Stratix 10 LL 40GbE IP Core Parameters 3. Getting Started 4. Functional Description 5. Reset 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Debugging the Link 9. Ethernet Toolkit Overview 10. Intel® Stratix® 10 Low Latency 40GbE IP Core User Guide Archives 11. Differences Between Intel Stratix 10 LL 40GbE IP Core and Low Latency 40GbE IP Core That Targets an Arria 10 Device 12. Document Revision History for Low Latency 40-Gbps Ethernet Intel Stratix 10 IP Core
1. Datasheet x
1.1. Intel Stratix 10 LL 40GbE IP Core Supported Features 1.2. Intel Stratix 10 LL 40GbE Core Device Family and Speed Grade Support 1.3. Resource Utilization 1.4. Release Information
1.2. Intel Stratix 10 LL 40GbE Core Device Family and Speed Grade Support x
1.2.1. Device Family Support 1.2.2. Intel Stratix 10 LL 40GbE IP Core Device Speed Grade Support
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying the Intel Stratix 10 LL 40GbE IP Core Parameters and Options 3.3. Simulating the IP Core 3.4. Generated File Structure 3.5. Integrating Your IP Core in Your Design 3.6. Intel Stratix 10 LL 40GbE IP Core Testbench 3.7. Compiling the Full Design and Programming the FPGA
3.5. Integrating Your IP Core in Your Design x
3.5.1. Pin Assignments 3.5.2. Adding the Transceiver PLL 3.5.3. Clock Requirements for 40GBASE-KR4/CR4 Variations 3.5.4. Adding the External TX MAC PLL 3.5.5. Placement Settings for the Intel Stratix 10 LL 40GbE Core
3.6. Intel Stratix 10 LL 40GbE IP Core Testbench x
3.6.1. Understanding the Testbench Behavior
4. Functional Description x
4.1. Intel Stratix 10 LL 40GbE Core Functional Description 4.2. User Interface to Ethernet Transmission
4.1. Intel Stratix 10 LL 40GbE Core Functional Description x
4.1.1. Intel Stratix 10 LL 40GbE Core TX MAC Datapath 4.1.2. Intel Stratix 10 LL 40GbE Core RX MAC Datapath 4.1.3. Link Fault Signaling Interface 4.1.4. Intel® Stratix® 10 Low Latency 40GBASE-KR4 IP Core Variations
4.1.1. Intel Stratix 10 LL 40GbE Core TX MAC Datapath x
4.1.1.1. Frame Padding 4.1.1.2. Preamble Insertion 4.1.1.3. Inter-Packet Gap Generation and Insertion 4.1.1.4. Frame Check Sequence (CRC-32) Insertion
4.1.2. Intel Stratix 10 LL 40GbE Core RX MAC Datapath x
4.1.2.1. IP Core Preamble Processing 4.1.2.2. IP Core Strict SFD Checking 4.1.2.3. Length/Type Field Processing 4.1.2.4. RX CRC Checking and Dynamic Forwarding
4.1.2.3. Length/Type Field Processing x
4.1.2.3.1. Length Checking
4.2. User Interface to Ethernet Transmission x
4.2.1. Order of Transmission 4.2.2. Bit Order For TX and RX Datapaths
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. Transceivers Signals 6.4. Transceiver Reconfiguration Signals 6.5. Avalon® Memory-Mapped Management Interface 6.6. Miscellaneous Status and Debug Signals 6.7. Reset Signals 6.8. Clocks 6.9. Flow Control Interface
7. Control, Status, and Statistics Register Descriptions x
7.1. Intel® Stratix® 10 LL 40GBASE-KR4/CR4 Registers 7.2. PHY Registers 7.3. TX MAC Registers 7.4. RX MAC Registers 7.5. Statistics Registers
7.5. Statistics Registers x
7.5.1. TX Statistics Registers 7.5.2. RX Statistics Registers
9. Ethernet Toolkit Overview x
9.1. Features
1. Datasheet
2. Intel Stratix 10 LL 40GbE IP Core Parameters
3. Getting Started
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. Ethernet Toolkit Overview
10. Intel® Stratix® 10 Low Latency 40GbE IP Core User Guide Archives
11. Differences Between Intel Stratix 10 LL 40GbE IP Core and Low Latency 40GbE IP Core That Targets an Arria 10 Device
12. Document Revision History for Low Latency 40-Gbps Ethernet Intel Stratix 10 IP Core

7.1. Intel® Stratix® 10 LL 40GBASE-KR4/CR4 Registers

Most 40GBASE-KR4 registers are 10GBASE-KR PHY registers of the Intel® Stratix® 10 10GBASE-KR PHY IP core. Exceptions are:

  • The register offsets of the 10GBASE-KR PHY registers are offset by negative 0x400 in the 40GBASE-KR4 variations of the Intel Stratix 10 LL 40GbE core. The Intel® Stratix® 10 10GBASE-KR PHY IP core registers begin at offset 0x4B0. In the Intel® Stratix® 10 LL 40GBASE-KR4 IP core, these registers begin at offset 0x0B0.
  • The LL 40GBASE-KR4 variations of the Intel Stratix 10 LL 40GbE core have additional 40GBASE-KR4 related registers and register fields.
  • The FEC error insertion feature requires that you program some Intel® Stratix® 10 device registers through the Intel® Stratix® 10 dynamic reconfiguration interface. The FEC error count is collected in other Intel® Stratix® 10 device registers that you access through the Intel® Stratix® 10 dynamic reconfiguration interface. You access the relevant Intel® Stratix® 10 device registers at offsets 0xBD through 0xE3 for Lane 0, 0x8BD through 0x8E3 for Lane 1, 0x10BD through 0x10E3 for Lane 2, and 0x18BD through 0x18E3 for Lane 3. The descriptions of the Intel® Stratix® 10 LL 40GBASE-KR4 registers that depend on these Intel® Stratix® 10 device registers provide the individual Intel® Stratix® 10 register information.
Table 24.   Intel® Stratix® 10 LL 40GBASE-KR4/CR4 Register Map
Word Offset Register Type
0xB0-0xBF General 40GBASE-KR4/CR4 registers
0xC0-0xCF Auto-negotiation registers
0xD0-0xEF Link training registers
Table 25.   Intel Stratix 10 LL 40GbE Core 40GBASE-KR4 Registers

Register fields not listed are Reserved.

To modify a field value in any Intel® Stratix® 10 LL 40GBASE-KR4 register, you must perform a read-modify-write operation to ensure you do not modify the values of any other fields in the register.

Address

Name

Bit

Description

HW Reset Value

Access

0x0B0

Reset SEQ [0] When set to 1, resets the 40GBASE-KR4/CR4 sequencer (auto rate detect logic), may initiate a PCS reconfiguration, and may restart auto-negotiation, link training or both if AN and LT are enabled (40GBASE-KR4/CR4 mode). SEQ Force Mode[3:0] forces these modes. This reset self clears.   RWSC
Disable AN Timer [1] Auto-negotiation disable timer. If disabled ( Disable AN Timer = 1) , AN may get stuck and require software support to remove the ABILITY_DETECT capability if the link partner does not include this feature (does not implement auto-negotiation). In addition, software may have to take the link out of loopback mode if the link is stuck in the ACKNOWLEDGE_DETECT state. To enable this timer set Disable AN Timer = 0.   RW
Disable LF Timer [2] When set to 1, disables the Link Fail timer. You can use this mode to characterize the link for link training. When set to 0, the Link Fault timer is enabled, and auto-negotation restarts at LF timer timeout.   RW
SEQ Force Mode[3:0] [7:4]

Forces the sequencer to a specific protocol. Must write the Reset SEQ bit (bit [0]) to 1 for the Force to take effect. The following encodings are defined:

  • 0000: No force
  • 0001: GigE mode (unsupported)
  • 0010: XAUI mode (unsupported)
  • 0100: 40GBASE-R4 mode (without auto-negotiation and without link training)
  • 0101: 40GBASE-KR4/CR4 mode
  • 1100: 40GBASE-R4 mode with FEC (without auto-negotiation and without link training)
4'b0 RW
Enable Stratix 10 Calibration [8] When set to 1, it enables the Intel® Stratix® 10 HSSI reconfiguration calibration as part of the PCS dynamic reconfiguration. 0 skips the calibration when the PCS is reconfigured. 1'b1 RW
LT Failure Response [12] When set to 1, LT failure causes the PHY to go into data mode (any of 40GBASE-R4, 40GBASE-KR4/CR4, or 40GBASE-R4 mode, as determined by current register and parameter settings). When set to 0, LT failure restarts auto-negotiation (if enabled). If auto-negotiation is not enabled, the PHY restarts LT. 1'b1 in simulation; 1'b0 in hardware RW
Assert KR FEC ability 171.0 [16] When set to 1, FEC is enabled (local FEC capability is on for auto-negotiation). When set to 0, FEC is disabled (local FEC capability is off for auto-negotiation). Resets to the Set FEC_Ability bit on power up or reset parameter value. Set FEC_Ability bit on power up or reset parameter value RW
Assert KR FEC request

[18]

When set to 1, enables the FEC request in auto-negotiation. When this bit changes, you must assert the Reset SEQ bit (0xB0[0]) to renegotiate with the new value. When set to 0, disables the FEC request. Resets to the Set FEC_Enable bit on power up or reset parameter value. Set FEC_Enable bit on power up or reset parameter value RW
0x0B1 SEQ Link Ready [0] When asserted, the Sequencer is indicating that the link is ready.   RO
SEQ AN timeout [1] When asserted, the Sequencer has had an auto-negotiation timeout. This bit is latched and is reset when the sequencer restarts auto-negotiation.   RO LH (latched high)
SEQ LT timeout [2] When set, indicates that the Sequencer has had a link-training timeout. This bit is latched and is reset when the sequencer restarts auto-negotiation.   RO LH
SEQ Reconfig Mode[5:0] [13:8] Specifies the Sequencer mode for PCS reconfiguration. The following modes are defined:
  • Bit 8, mode[0]: AN mode
  • Bit 9, mode[1]: LT Mode
  • Bit 10, mode[2]: 40G data mode
  • Bit 11, mode[3]: Reserved for GigE
  • Bit 12, mode[4]: Reserved for XAUI
  • Bit13, mode[5]: 40G FEC data mode
   
KR4 FEC ability 170.0 [16] When set to 1, indicates that the 40GBASE-KR4/CR4 PHY supports FEC. For more information, refer to Clause 45.2.1.84 of IEEE 802.3-2012. Include FEC sublayer parameter value RO
KR4 FEC err ind ability 170.1 [17] When set to 1, indicates that the 40GBASE-KR4/CR4 PHY is capable of reporting FEC decoding errors to the PCS. For more information, refer to Clause 74.8.3 of IEEE 802.3-2012. Include FEC sublayer parameter value RO
FEC Block Lock [23:20]

FEC Block Lock for lanes [3:0]: bit [20] is FEC block lock for lane 0, bit [21] is FEC block lock for lane 1, bit [22] is FEC block lock for lane 2, and bit [23] is FEC block lock for lane 3.

4'b0 RO
0xB2 KR FEC TX Error Insert, Lane 0 11 Writing a 1 inserts one error pulse into the TX FEC for lane 0, depending on the Transcoder and Burst error settings for lane 0.

You must select these settings through the Intel® Stratix® 10 dynamic reconfiguration interface to the Intel® Stratix® 10 device registers before you write a 1 to the KR FEC TX Error Insert, Lane 0 bit. To select these settings for Lane 0, perform a read-modify-write operation sequence at register offset 0xBD.

You select a Transcoder error by setting the transcode_err bit (bit 0), resetting the burst_err bit (bit 1), resetting the burst_err_len field (bits [7:4]), and leaving the remaining bits at their previous values.

You select a Burst error by setting the burst_err bit (bit 1), specifying the burst error length in the burst_err_len field (bits [7:4]), resetting the transcode_err bit (bit 0), and leaving the remaining bits at their previous values.

1'b0 RWSC
RCLR_ERRBLK_CNT, Lane 0 12 Writing a 1 resets the error block counters.Writing a 0 causes counting to resume.

Each lane has a 32-bit corrected error block counter and a 32-bit uncorrected error block counter in the Arria 10 device registers. Refer to Clause 74.8.4.1 and Clause 74.8.4.2 of IEEE Std 802.3-2012.

For Lane 0, the corrected error block counter is in the Intel® Stratix® 10 device registers you access through the Intel® Stratix® 10 dynamic reconfiguration interface at offsets 0xDC to 0xDF: blkcnt_corr[31:0] is in {0xDF[7:0],0xDE[7:0],0xDD[7:0],0xDC[7:0]}.

For Lane 0, the uncorrected error block counter is in the Intel® Stratix® 10 device registers you access through the Intel® Stratix® 10 dynamic reconfiguration interface at offsets 0xE0 to 0xE3: blkcnt_uncorr[31:0] is in {0xE3[7:0],0xE2[7:0],0xE1[7:0],0xE0[7:0]}.

  RW

0x0B5

Register 0xB2 refers to Lane 0. This register is the equivalent of register 0xB2 for Lane 1. The relevant FEC error Intel® Stratix® 10 device registers for Lane 1 are at 0x8BD through 0x8E3 (additional offset of 0x800).

RW

0x0B8

This register is the equivalent of register 0xB2 for Lane 2. The relevant FEC error Intel® Stratix® 10 device registers for Lane 2 are at 0x10BD through 0x10E3 (additional offset of 0x1000 compared to the Lane 0 device registers).

RW

0x0BB

This register is the equivalent of register 0xB2 for Lane 3. The relevant FEC error Intel® Stratix® 10 device registers for Lane 3 are at 0x18BD through 0x18E3 (additional offset of 0x1800 compared to the Lane 0 device registers).

RW

0x0C0

AN enable [0] When set to 1, enables Auto Negotiation function. When set to 0, disables the Auto Negotiation state variable mr_autoneg_enable described in Clause 73.10.1 in IEEE 802.3-2012. For additional information, refer to Clause 45.2.7, Management Register Requirements, in IEEE 802.3-2012. 1'b1 RW
AN base pages ctrl [1] When set to 1, the user base pages are enabled. You can send any arbitrary data via the user base page low or high bits. When set to 0, the user base pages are disabled and the state machine generates the base pages to send.   RW
AN next pages ctrl [2] When set to 1, the user next pages are enabled. You can send any arbitrary data via the user next page low or high bits. When set to 0, the user next pages are disabled. The state machine generates the null message to send as next pages.   RW
Local device remote fault [3] When set to 1, the local device signals Remote Faults in the Auto Negotiation pages. When set to 0, the local device does not signal Remote Faults.   RW
Force TX nonce value [4] When set to 1, forces the TX nonce value to support some UNH testing modes. Reset this bit to the value of 0 for normal operation.   RW
Override AN Parameters Enable [5] When set to 1, overrides the AN_TECH (Enable 40GBASE-CR4 Technology Ability and Include FEC sublayer), AN_FEC (Set FEC_Ability bit on power up or reset and Set FEC_Enable bit on power up or reset), and AN_PAUSE (Pause ability–C0 and Pause ability–C1) parameters and uses the bits in 0xC3[30:16] instead. You must reset the Sequencer (0xB0[0]) to reconfigure and restart in Auto Negotiation mode.   RW
Ignore nonce field [7] When set to 1, tells the IP core to ignore the TX nonce field. This mode supports auto-negotiation when the IP core is in loopback mode.   RW
0x0C1 Reset AN [0] When set to 1, resets all the 40GBASE-KR4/CR4 auto-negotiation state machines. This bit is self-clearing. When set to 0, disables the Auto Negotiation state variable mr_main_reset (7.0.15) described in Clause 73.10.1 in IEEE 802.3-2012. For additional information, refer to Clause 45.2.7, Management Register Requirements, in IEEE 802.3-2012.   RWSC
Restart AN TX SM [4] When set to 1, restarts the 40GBASE-KR4/CR4 TX state machines. This bit is self-clearing. This bit is active only when the TX state machine is in the Auto Negotiation state. When set to 0, disables the Auto Negotiation state variable mr_restart_negotiation (7.0.9) described in Clause 73.10.1 in IEEE 802.3-2012. For more information, refer to 7.0.9 in Clause 45.2.7, Management Register Requirements, in IEEE 802.3-2012   RWSC
AN Next Page [8] When asserted, new next page info is ready to send. The data is in the XNP TX registers. When 0, the TX interface sends null pages. This bit is self-clearing. Next Page (NP) is encoded in bit D15 of Link Codeword. For more information, refer to Clause 73.6.9 and 7.16.15 of Clause 45.2.7.6 of IEEE 802.3-2012.   RWSC
0x0C2 AN page received [1] When set to 1, a page has been received. When 0, a page has not been received. The current value clears when the register is read. For more information, refer to 7.1.6 (state variable mr_page_rx) in Clause 73.8 of IEEE 802.3-2012.   RO LH
AN Complete [2] When asserted, auto-negotiation has completed. When 0, auto-negotiation is in progress. For more information, refer to 7.1.5 (state variable mr_autoneg_complete) in Clause 73.8 of IEEE 802.3-2012.   RO
AN ADV Remote Fault [3] When set to 1, fault information has been sent to the link partner. When 0, a fault has not occurred. The current value clears when the register is read. Remote Fault (RF) is encoded in bit D13 of the base Link Codeword. For more information, refer to Clause 73.6.7 of and 7.16.13 (state variable mr_adv_ability) of IEEE 802.3-2012.   RO LH
AN RX SM Idle [4] When set to 1, the auto-negotiation state machine is in the idle state. Incoming data is not Clause 73 compatible. When 0, the auto-negotiation is in progress.   RO
AN Ability [5] When set to 1, the transceiver PHY is able to perform auto-negotiation. When set to 0, the transceiver PHY is not able to perform auto-negotiation. If your IP core variation includes auto-negotiation, this bit is tied to 1. For more information, refer to 7.1.3 and 7.48.0 in Clause 45 of IEEE 802.3-2012.   RO
AN Status [6] When set to 1, the link is up. When 0, the link is down. The current value clears when the register is read. For more information, refer to 7.1.2 of Clause 45 of IEEE 802.3-2012.   RO LL (latched low)
LP AN Ability [7] When set to 1, the link partner is able to perform auto-negotiation. When set to 0, the link partner is not able to perform auto-negotiation. For more information, refer to 7.1.0 in Clause 45 of IEEE 802.3-2012.   RO
FEC negotiated – enable FEC from SEQ [8] When set to 1, the transceiver PHY has negotiated to perform FEC. When set to 0, the transceiver PHY has not negotiated to perform FEC. For more information, refer to 7.48.4 in Clause 45 of IEEE 802.3-2012.   RO
Seq AN Failure [9] When set to 1, a sequencer auto-negotiation failure has been detected. When set to 0, an auto-negotiation failure has not been detected.   RO
KR4 AN Link Ready [5:0] [17:12] Provides a one-hot encoding of an_receive_idle = true and link status for the supported link as described in Clause 73.10.1. The following encodings are defined:
  • 6'b000000: 1000BASE-KX
  • 6'b000001: 10GBASE-KX4
  • 6'b000100: 10GBASE-KR
  • 6'b001000: 40GBASE-KR4
  • 6'b010000: 40GBASE-CR4
  • 6'b100000: 100GBASE-CR10

The only valid values for the LL 40GBASE-KR4/CR4 IP core are 6'b001000: 40GBASE-KR4 and 6'b010000: 40GBASE-CR4.

6'b001000 RO

0x0C3

 User base page low [15:0] The Auto Negotiation TX state machine uses these bits if the Auto Negotiation base pages control bit (0xC0[1]) is set. The following bits are defined:
  • [4:0]: Selector
  • [9:5]: Echoed nonce bits which are set by the state machine
  • [12:10]: Pause bits
  • [13]: Remote Fault bit
  • [14]: ACK which is controlled by the SM
  • [15]: Next page bit
Bit [49], the PRBS bit, is generated by the Auto Negotiation TX state machine. 		  RW
Override AN_TECH[5:0] [21:16]

AN_TECH value with which to override the current value. The following bits are defined:

  • [16]: AN_TECH[0]= 1000BASE-KX
  • [17]: AN_TECH[1] = XAUI
  • [18]: AN_TECH[2] = 10GBASE-KR
  • [19]: AN_TECH[3] = 40G
  • [20]: AN_TECH[4] = CR-4
  • [21]: AN_TECH[5] = 100G
You must set 0x4C0[5] for the override to take effect. 		  RW
Override AN_FEC[1:0] [25:24] AN_FEC value with which to override the current value. The following bits are defined:
  • [24]: AN_ FEC[0] = Capability
  • [25]: AN_ FEC[1] = Request
You must set 0x4C0[5] for the override to take effect. 		  RW
Override AN_PAUSE[2:0] [30:28] AN_PAUSE value with which to override the current value. The following bits are defined:
  • [28]: AN_PAUSE[0] = Pause Ability
  • [29]: AN_PAUSE[1] = Asymmetric Direction
  • [30]: AN_PAUSE[2] = Reserved
You must set 0x4C0[5] for the override to take effect. 		  RW

0x0C4

 User base page high [31:0] The Auto Negotiation TX state machine uses these bits if the Auto Negotiation base pages ctrl bit (0xC0[1]) is set. The following bits are defined:
  • [31:30]: Correspond to page bits [47:46] which are the FEC bits.
  • [29:5]: Correspond to page bits [45:21] which are the technology ability bits.
  • [4:0]: Correspond to bits [20:16] which are TX nonce bits.
Bit [49], the PRBS bit, is generated by the Auto Negotiation TX state machine. 		  RW
0x0C5 User Next page low [15:0] The Auto Negotiation TX state machine uses these bits if the Auto Negotiation next pages control bit (0xC0[2]) is set. The following bits are defined:
  • [11]: Toggle bit
  • [12]: ACK2 bit
  • [13]: MP bit
  • [14]: ACK which is controlled by the SM
  • [15]: Next page bit
For more information, refer to Clause 73.7.7.1 Next Page encodings of IEEE 802.3-2012. Bit [49], the PRBS bit, is generated by the Auto Negotiation TX state machine. 		  RW
0x0C6 User Next page high [31:0] The Auto Negotiation TX state machine uses these bits if the Auto Negotiation next pages ctrl bit (0xC0[2]) is set. Bits [31:0] correspond to page bits [47:16]. Bit [49], the PRBS bit, is generated by the Auto Negotiation TX state machine.   RW
0x0C7 LP base page low [15:0] The Auto Negotiation RX state machine receives these bits from the link partner. The following bits are defined:
  • [4:0]: Selector
  • [9:5]: Echoed nonce bits which are set by the state machine
  • [12:10]: Pause bits
  • [13]: Remote Fault bit
  • [14]: ACK which is controlled by the SM
  • [15]: Next page bit
Bit [49], the PRBS bit, is not included. 		  RO
0x0C8 LP base page high [31:0] The Auto Negotiation RX state machine receives these bits from the link partner. The following bits are defined:
  • [31:30]: Correspond to page bits [47:46] which are the FEC bits.
  • [29:5]: Correspond to page bits [45:21] which are the technology ability bits.
  • [4:0]: Correspond to bits [20:16] which are TX nonce bits.
Bit [49], the PRBS bit, is not included. 		  RO
0x0C9 LP Next page low [15:0] The Auto Negotiation RX state machine receives these bits from the link partner. The following bits are defined:
  • [11]: Toggle bit
  • [12]: ACK2 bit
  • [13]: MP bit
  • [14]: ACK which is controlled by the SM
  • [15]: Next page bit
For more information, refer to Clause 73.7.7.1 Next Page encodings of IEEE 802.3-2012. Bit [49], the PRBS bit, is not included. 		  RO
0x0CA LP Next page high [31:0] The Auto Negotiation RX state machine receives these bits from the link partner. Bits [31:0] correspond to page bits [47:16]. Bit [49], the PRBS bit, is not included.   RO

0x0CB

AN LP ADV Tech_A[24:0] [24:0] Received technology ability field bits of Clause 73 Auto Negotiation. Provides a one-hot encoding to specify one of the following protocols:
  • Bit [0]: 1000BASE-KX
  • Bit [1]: 10GBASE-KX4
  • Bit [2]: 10GBASE-KR
  • Bit [3]: 40GBASE-KR4
  • Bit [4]: 40GBASE-CR4
  • Bit [5]: 100GBASE-CR10
  • Bits [24:6] are reserved

The only valid values for the LL 40GBASE-KR4 IP core are 'b001000: 40GBASE-KR4 and 'b010000: 40GBASE-CR4.

25'b0

RO

AN LP ADV FEC_F[1:0] [26:25] Received FEC ability bits FEC (F0:F1) is encoded in bits D46:D47 of the base Link Codeword. F0 is FEC ability. F1 is FEC requested.   RO
AN LP ADV Remote Fault [27] Received Remote Fault (RF) ability bits. RF is encoded in bit D13 of the base link codeword in Clause 73 AN.   RO
AN LP ADV Pause Ability_C[2:0] [30:28] Received pause ability bits. Pause (C0:C1) is encoded in bits D11:D10 of the base link codeword in Clause 73 AN as follows:
  • C0 is the same as PAUSE as defined in Annex 28B
  • C1 is the same as ASM_DIR as defined in Annex 28B
  • C2 is reserved
  RO
0x0D0 Link training enable [0] When set to 1, enables the 40GBASE-KR4/CR4 start-up protocol. When 0, disables the 40GBASE-KR4/CR4 start-up protocol. The default value is 1. For more information, refer to Clause 72.6.10.3.1 and 10GBASE-KR PMD control register bit (150.1) of IEEE 802.3-2012. 1'b1 RW
dis_max_wait_tmr [1] When set to 1, disables the LT max_wait_timer. Used for characterization mode when setting much longer BER timer values.   RW
main_step_cnt[3:0] [7:4] Specifies the number of equalization steps for each main tap update. Devices have about 40 steps, so a value of 2 provides about 20 settings for the internal algorithm to test. A value of 3 provides 13 settings. The valid range is 1-15. 4'b0001 RW
prepost_step_cnt[3:0] [11:8] Specifies the number of equalization steps for each pre- and post-tap update. Devices have 16-31 steps, a smaller range than for main_step_cnt. Set this value to provide fewer settings than for the main tap. 4'b0001 RW
equal_cnt[2:0] [14:12]

Number to make error counts equal. Adds hysteresis to the error count to avoid local minimums. The following values are defined:

  • 3'b000 = 0
  • 3'b001 = 2
  • 3'b010 = 4
  • 3'b011 = 8
  • 3'b100 = 16
  • 3'b101 = 32
  • 3'b110 = 64
  • 3'b111 = 128
 3'b101 RW
disable Initialize PMA on max_wait_timeout [15] When set to 1, PMA values (VOD, Pre-tap, Post-tap) are not initialized upon entry into the Training_Failure state. This happens when max_wait_timer_done, which sets training_failure = true (0xD2[3])). Used for UNH testing. When set to 0, PMA values are initialized upon entry into Training_Failure state. Refer to Figure 72-5 of IEEE 802.3-2012 for more details. 1'b0  
Ovride LP Coef Enable [16] When set to 1, overrides the link partner's equalization coefficients; software changes the update commands sent to the link partner TX equalizer coefficients. When set to 0, uses the Link Training logic to determine the link partner coefficients. Used with 0x0D1[7:4] and with bits[7:0] of 0x0D4 through 0x0D7. 1'b0 RW
Ovride Local RX Coef Enable [17] When set to 1, overrides the local device equalization coefficients generation protocol. When set, the software changes the local TX equalizer coefficients. When set to 0, uses the update command received from the link partner to determine local device coefficients. Used with 0x0D1[11:8] and bits[23:16] of 0x0D4 through 0x0D7. 1'b0 RW

0x0D1

Restart Link training, Lane 0 [0]

When set to 1, resets the 40GBASE-KR4 start-up protocol. When set to 0, continues normal operation. This bit self clears. Refer to the state variable mr_restart_training as defined in Clause 72.6.10.3.1 and 10GBASE-KR PMD control register bit (150.0) in IEEE Std 802.3-2012.

1'b0

RW SC
Restart Link training, Lane 1 [1] This bit is the equivalent of register 0xD1[0] for Lane 1. 1'b0 RW SC
Restart Link training, Lane 2 [2]

This bit is the equivalent of register 0xD1[0] for Lane 2.

1'b0

RW SC
Restart Link training, Lane 3 [3]

This bit is the equivalent of register 0xD0[0] for Lane 3.

1'b0

RW SC

0x0D1

Updated TX Coef new, Lane 0 [4]

When set to 1, indicates that new link partner coefficients are available to send. The LT logic starts sending the new values set in 0xD4[7:0] to the remote device. When set to 0, continues normal operation. This bit self clears.

This override of normal operation can only occur if 0xD0[16] (Ovride LP Coef enable) has the value of 1. If 0xD0[16] has the value of 0, this register field (0xD1[4]) has no effect.

1'b0

RW SC

Updated TX Coef new, Lane 1 [5] This bit is the equivalent of register 0xD1[4] for Lane 1. If set to the value of 1, LT logic sends the new values set in 0xE1[7:0] to the remote device.[6]    
Updated TX Coef new, Lane 2  

[6This bit is the equivalent of register 0xD1[4] for Lane 2. If set to the value of 1, LT logic sends the new values set in 0xE5[7:0] to the remote device.

1'b0

RW SC
Updated TX Coef new, Lane 3 [7]

This bit is the equivalent of register 0xD1[4] for Lane 3. If set to the value of 1, LT logic sends the new values set in 0xE9[7:0] to the remote device.

1'b0

RW SC

0x0D1

Updated RX Coef new, Lane 0 [8]

When set to 1, indicates that new local device coefficients are available for Lane 1. The LT logic changes the local TX equalizer coefficients as specified in 0xD4[23:16]. When set to 0, continues normal operation. This bit self clears.

This override of normal operation can only occur if 0xD0[17] (Ovride Local RX Coef enable) has the value of 1. If 0xD0[17] has the value of 0, this register field (0xD1[8]) has no effect.

1'b0

RW

Updated RX Coef new, Lane 1 [9] This bit is the equivalent of register 0xD1[8] for Lane 1. If set to the value of 1, LT logic changes the local TX equalizer coefficients as specified in 0xE1[23:16].    
Updated RX Coef new, Lane 2 [10]

This bit is the equivalent of register 0xD1[8] for Lane 2. If set to the value of 1, LT logic changes the local TX equalizer coefficients as specified in 0xE5[23:16].

1'b0

RW

Updated RX Coef new, Lane 3 [11]

This bit is the equivalent of register 0xD1[8] for Lane 3. If set to the value of 1, LT logic changes the local TX equalizer coefficients as specified in 0xE9[23:16].

1'b0

RW

0x0D2

Link Trained - Receiver status, Lane 0 [0] When set to 1, the receiver is trained and is ready to receive data. When set to 0, receiver training is in progress. For more information, refer to the state variable rx_trained as defined in Clause 72.6.10.3.1 of IEEE 802.3-2012.   RO
Link Training Frame lock, Lane 0 [1] When set to 1, the training frame delineation has been detected. When set to 0, the training frame delineation has not been detected. For more information, refer to the state variable frame_lock as defined in Clause 72.6.10.3.1 of IEEE 802.3-2012.   RO
Link Training Start-up protocol status, Lane 0 [2] When set to 1, the start-up protocol is in progress. When set to 0, start-up protocol has completed. For more information, refer to the state variable training as defined in Clause 72.6.10.3.1 of IEEE 802.3-2012.   RO
Link Training failure, Lane 0 [3] When set to 1, a training failure (max_wait_timeout) has been detected. When set to 0, a training failure has not been detected. For more information, refer to the state variable training_failure as defined in Clause 72.6.10.3.1 of IEEE 802.3-2012.   RO
Link Training Frame lock Error, Lane 0 [5] When set to 1, indicates a frame lock was lost during Link Training. If the tap settings specified by the fields of 0xD5 are the same as the initial parameter value, the frame lock error was unrecoverable. When set to 0, frame lock was not lost.   RO

Link Trained - Receiver status, Lane 1

Link Training Frame lock, Lane 1

Link Training Start-up protocol status, Lane 1

Link Training failure, Lane 1

Link Training Frame lock Error, Lane 1

[13],[11:8]

Register bits 0xD2[5] and [3:0] refer to Lane 0. These bits are the equivalent of 0xD2[5] and [3:0], respectively, for Lane 1.

For Link Training Frame lock Error, Lane 1, if the tap settings specified by the fields of 0xE2 are the same as the initial parameter value, the frame lock error was unrecoverable.

RO

Link Trained - Receiver status, Lane 2

Link Training Frame lock, Lane 2

Link Training Start-up protocol status, Lane 2

Link Training failure, Lane 2

Link Training Frame lock Error, Lane 2

[21],[19:16]

These bits are the equivalent of 0xD2[5] and [3:0], respectively, for Lane 2.

For Link Training Frame lock Error, Lane 2, if the tap settings specified by the fields of 0xE6 are the same as the initial parameter value, the frame lock error was unrecoverable.

RO

Link Trained - Receiver status, Lane 3

Link Training Frame lock, Lane 3

Link Training Start-up protocol status, Lane 3

Link Training failure, Lane 3

Link Training Frame lock Error, Lane 3

[29],[27:24]

These bits are the equivalent of 0xD2[5] and [3:0], respectively, for Lane 3.

For Link Training Frame lock Error, Lane 3, if the tap settings specified by the fields of 0xEA are the same as the initial parameter value, the frame lock error was unrecoverable.

RO

0x0D3 ber_time_frames [9:0] Specifies the number of training frames to examine for bit errors on the link for each step of the equalization settings. Used only when ber_time_k_frames has the value of 0. The following values are defined:
  • A value of 2 is about 103 bytes
  • A value of 20 is about 104 bytes
  • A value of 200 is about 105 bytes
0x003 in simulation; 0 in hardware RW
ber_time_k_frames [19:10] Specifies the number of thousands of training frames to examine for bit errors on the link for each step of the equalization settings. Set ber_time_m_frames to the value of 0 for time/bits to match the following values:
  • A value of 3 is about 107 bits = about 1.3 ms
  • A value of 25 is about 108 bits = about 11ms
  • A value of 250 is about 109 bits = about 11 0ms
0 in simulation; 0x00F in hardware RW
ber_time_m_frames [29:20] Specifies the number of millions of training frames to examine for bit errors on the link for each step of the equalization settings. Set ber_time_k_frames to the value of 0x3E8 (decimal 1000) for time/bits to match the following values:
  • A value of 3 is about 1010 bits = about 1.3 seconds
  • A value of 25 is about 10 11 bits = about 11 seconds
  • A value of 250 is about 1012 bits = about 110 seconds
10'b0 RW
0x0D4 LD coefficient update[5:0], Lane 0 [5:0] Reflects the contents of the first 16-bit word of the control channel that the IP core most recently sent on Lane 0. Normally, the bits in this register are read-only; however, when you override training by setting the Ovride LP Coef enable control bit (0x0D0 bit [16]), these bits become writable. The following fields are defined:
  • [5: 4]: Coefficient (+1) update
    • 2'b11: Reserved
    • 2'b01: Increment
    • 2'b10: Decrement
    • 2'b00: Hold
  • [3:2]: Coefficient (0) update (same encoding as [5:4])
  • [1:0]: Coefficient (-1) update (same encoding as [5:4])

Before you can send these bits, you must enable the override in 0x0D0[16] and also signal a new word in 0x0D1[4].

For more information, refer to bit 10G BASE-KR LD coefficient update register bits (154.5:0) in Clause 45.2.1.80.3 of IEEE 802.3-2012. 		  RO/RW
LD Initialize Coefficients, Lane 0 [6] When set to 1, requests the link partner coefficients be set to configure the TX equalizer for Lane 0 to its INITIALIZE state. When set to 0, continues normal operation on Lane 0. The IP core sends this value in bit 12 of the control channel on Lane 0. For more information, refer to 10G BASE-KR LD coefficient update register bits (154.12) in Clause 45.2.1.80.3 and Clause 72.6.10.2.3.2 of IEEE 802.3-2012.   RO/RW
LD Preset Coefficients, Lane 0 [7] When set to 1, requests the link partner coefficients be set to a state where equalization is turned off on Lane 0. When set to 0 the link operates normally. The IP core sends this value in bit 13 of the control channel on Lane 0. For more information, refer to 10G BASE-KR LD coefficient update register bit (154.13) in Clause 45.2.1.80.3 and Clause 72.6.10.2.3.2 of IEEE 802.3-2012.   RO/RW
LD coefficient status[5:0], Lane 0 [13:8] Status report register for the contents of the second, 16-bit word of the control channel that the IP core most recently sent on Lane 0. The following fields are defined:
  • [5:4]: Coefficient (+1)
    • 2'b11: Maximum
    • 2'b01: Minimum
    • 2'b10: Updated
    • 2'b00: Not updated
  • [3:2]: Coefficient (0) (same encoding as [5:4])
  • [1:0]: Coefficient (-1) (same encoding as [5:4])
For more information, refer to 10G BASE-KR LD status report register bit (155.5:0) in Clause 45.2.1.81 of IEEE 802.3-2012. 		  RO
Link Training ready - LD Receiver ready, Lane 0 [14] When set to 1, the local device receiver has determined that training is complete and is prepared to receive data. The IP core sends this value in bit 15 of the control channel on Lane 0. When set to 0, the local device receiver is requesting that training continue. Values for the receiver ready bit are defined in Clause 72.6.10.2.4.4. For more information, refer to 10G BASE-KR LD status report register bit (155.15) in Clause 45.2.1.81 of IEEE 802.3-2012.   RO
LP Coefficient Update[5:0], Lane 0 [21:16] Reflects the contents of the first 16-bit word of the control channel that the IP core most recently received on Lane 0.

Normally the bits in this register are read only; however, when training is disabled by setting low the Link Training enable control bit (Link training enable at 0xD0[0]), these bits become writable. The following fields are defined:

  • [5: 4]: Coefficient (+1) update
    • 2'b11: Reserved
    • 2'b01: Increment
    • 2'b10: Decrement
    • 2'b00: Hold
  • [3:2]: Coefficient (0) update (same encoding as [5:4])
  • [1:0]: Coefficient (-1) update (same encoding as [5:4])

Before you can send these bits, you must enable the override in 0x0D0 bit [17] and also signal a new word in 0x0D2 bit [8].

For more information, refer to bit 10G BASE-KR LP coefficient update register bits (152.5:0) in Clause 45.2.1.78.3 of IEEE 802.3-2012.

  RO/RW
LP Initialize Coefficients, Lane 0 [22] When set to 1, the local device transmit equalizer coefficients are set to the INITIALIZE state. When set to 0, normal operation continues. The function and values of the initialize bit are defined in Clause 72.6.10.2.3.2. The IP core receives this value on Lane 0 in bit 12 of the control channel. For more information, refer to 10G BASE-KR LP coefficient update register bits (152.12) in Clause 45.2.1.78.3 of IEEE 802.3-2012.   RO/RW
LP Preset Coefficients, Lane 0 [23] When set to 1, the local device TX coefficients are set to a state where equalization is turned off. Preset coefficients are used. When set to 0, the local device operates normally. The IP core receives this value on Lane 0 in bit 13 of the control channel. The function and values of the preset bit are defined in 72.6.10.2.3.1. The function and values of the initialize bit are defined in Clause 72.6.10.2.3.1. For more information, refer to 10G BASE-KR LP coefficient update register bits (152.13) in Clause 45.2.1.78.3 of IEEE 802.3-2012.   RO/RW
LP coefficient status[5:0], Lane 0 [29:24] Status report register reflects the contents of the second, 16-bit word of the control channel that the IP core most recently received on Lane 0. The following fields are defined:
  • [5:4]: Coefficient (+1)
    • 2'b11: Maximum
    • 2'b01: Minimum
    • 2'b10: Updated
    • 2'b00: Not updated
  • [3:2]: Coefficient (0) (same encoding as [5:4])
  • n [1:0]: Coefficient (-1) (same encoding as [5:4])
For more information, refer to 10G BASE-KR LP status report register bits (153.5:0) in Clause 45.2.1.79 of IEEE 802.3-2012. 		  RO
LP Receiver ready, Lane 0 [30] When set to 1, the link partner receiver has determined that training is complete and is prepared to receive data. When set to 0, the link partner receiver is requesting that training continue. The IP core receives this value on Lane 0 in bit 15 of the control channel.

Values for the receiver ready bit are defined in Clause 72.6.10.2.4.4. For more information, refer to 10G BASE-KR LP status report register bits (153.15) in Clause 45.2.1.79 of IEEE 802.3-2012.

  RO
0x0D5 LT VOD setting, Lane 0 [4:0] Stores the most recent TX VOD setting trained by the link partner's RX based on the LT coefficient update logic driven by Clause 72. It reflects Link Partner commands to fine-tune the TX taps.   RO
LT Post-tap setting, Lane 0 [13:8] Stores the most recent TX post-tap setting trained by the link partner’s RX based on the LT coefficient update logic driven by Clause 72. It reflects Link Partner commands to fine-tune the TX taps.   RO
LT Pre-tap setting, Lane 0 [20:16] Stores the most recent TX pre-tap setting trained by the link partner’s RX based on the LT coefficient update logic driven by Clause 72. It reflects Link Partner commands to fine-tune the TX taps.   RO
0x0D6 LT VODMAX ovrd, Lane 0 [4:0] Override value for the VMAXRULE parameter on Lane 0. When enabled, this value substitutes for the VMAXRULE to allow channel-by-channel override of the device settings. This only effects the local device TX output for the channel specified.

This value must be greater than the INITMAINVAL parameter for proper operation. Note this also overrides the PREMAINVAL parameter value.

0x1C (28 decimal) for simulation; 0 for hardware RW
LT VODMAX ovrd Enable, Lane 0 [5] When set to 1, enables the override value for the VMAXRULE parameter stored in the LT VODMAX ovrd, Lane 0 register field. 1 for simulation; 0 for hardware RW
LT VODMin ovrd, Lane 0 [12:8] Override value for the VODMINRULE parameter on Lane 0. When enabled, this value substitutes for the VMINRULE to allow channel-by-channel override of the device settings. This override only effects the local device TX output for this channel.

The value to be substituted must be less than the INITMAINVAL parameter and greater than the VMINRULE parameter for proper operation.

0x19 (25 decimal) for simulation; 0 for hardware RW
LT VODMin ovrd Enable, Lane 0 [13] When set to 1, enables the override value for the VODMINRULE parameter stored in the LT VODMin ovrd, Lane 0 register field. 1 for simulation; 0 for hardware RW
LT VPOST ovrd, Lane 0 [21:16] Override value for the VPOSTRULE parameter on Lane 0. When enabled, this value substitutes for the VPOSTRULE to allow channel-by-channel override of the device settings. This override only effects the local device TX output for this channel.

The value to be substituted must be greater than the INITPOSTVAL parameter for proper operation.

6 for simulation; 0 for hardware RW
LT VPOST ovrd Enable, Lane 0 [22] When set to 1, enables the override value for the VPOSTRULE parameter stored in the LT VPOST ovrd, Lane 0 register field. 1 for simulation; 0 for hardware RW
LT VPre ovrd, Lane 0 [28:24] Override value for the VPRERULE parameter on Lane 0. When enabled, this value substitutes for the VPOSTRULE to allow channel-by-channel override of the device settings. This override only effects the local device TX output for this channel.

The value to be substituted must be greater than the INITPREVAL parameter for proper operation.

4 for simulation; 0 for hardware RW
LT VPre ovrd Enable, Lane 0 [29] When set to 1, enables the override value for the VPRERULE parameter stored in the LT VPre ovrd, Lane 0 register field. 1 for simulation; 0 for compilation RW

0xE0

Register 0xD3 refers to Lane 0. This register, register 0xE0, is the equivalent of register 0xD3 for Lane 1 link training.

RW

0xE1

Register 0xD4 refers to Lane 0. This register, register 0xE1, is the equivalent of register 0xD4 for Lane 1 link training.

R / RW

0xE2

Register 0xD5 refers to Lane 0. This register, register 0xE2, is the equivalent of register 0xD5 for Lane 1 link training.

RO

0xE3

Register 0xD6 refers to Lane 0. This register, register 0xE3, is the equivalent of register 0xD6 for Lane 1 link training..

RW

0xE4

This register is the equivalent of register 0xD3 for Lane 2 link training.

RW

0xE5

This register is the equivalent of register 0xD4 for Lane 2 link training.

R / RW

0xE6

This register is the equivalent of register 0xD5 for Lane 2 link training.

RO

0xE7

This register is the equivalent of register 0xD6 for Lane 2 link training.

RW

0xE8

This register is the equivalent of register 0xD3 for Lane 3 link training.

RW

0xE9

This register is the equivalent of register 0xD4 for Lane 3 link training.

R / RW

0xEA

This register is the equivalent of register 0xD5 for Lane 3 link training.

RO

0xEB

This register is the equivalent of register 0xD6 for Lane 3 link training.

RW

Level Two Title