Visible to Intel only — GUID: lbl1458336951727
Ixiasoft
1. About the Low Latency 40G Ethernet Core
2. Stratix® 10 Low Latency 40G Ethernet IP Core Parameters
3. Getting Started
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. Ethernet Toolkit Overview
10. Stratix® 10 Low Latency 40GbE IP Core User Guide Archives
11. Differences Between Stratix® 10 Low Latency 40G Ethernet IP Core and Low Latency 40G Ethernet IP Core That Targets an Arria 10 Device
12. Document Revision History for Stratix® 10 Low Latency 40G Ethernet User Guide
3.1. Installing and Licensing Intel® FPGA IP Cores
3.2. Specifying the Stratix® 10 LL 40GbE IP Core Parameters and Options
3.3. Simulating the IP Core
3.4. Generated File Structure
3.5. Integrating Your IP Core in Your Design
3.6. Stratix® 10 Low Latency 40G Ethernet IP Core Testbench
3.7. Compiling the Full Design and Programming the FPGA
Visible to Intel only — GUID: lbl1458336951727
Ixiasoft
7.3. TX MAC Registers
Addr | Name | Description | Reset | Access |
---|---|---|---|---|
0x400 | TXMAC_REVID | TX MAC revision ID for 40GbE TX MAC CSRs. |
0x0627 2016 |
RO |
0x401 | TXMAC_SCRATCH | Scratch register available for testing. | 0x0000 0000 | RW |
0x402 | TXMAC_NAME_0 | First 4 characters of module variation identifier string, "40gMACTxCSR". |
0x3430 674D | RO |
0x403 | TXMAC_NAME_1 | Next 4 characters of IP core variation identifier string, "ACTx". |
0x4143 5278 | RO |
0x404 | TXMAC_NAME_2 | Final 4 characters of IP core variation identifier string, "0CSR". The "0" is unprintable. | 0x0043 5352 | RO |
0x405 | LINK_FAULT | Link Fault Configuration Register. The following bits are defined:
|
28'hX_4'b0001 3 | RW |
0x406 | IPG_COL_REM | Specifies the number of IDLE columns to be removed in every Alignment Marker period to compensate for alignment marker insertion. You can program this register to a larger value than the default value, for clock compensation. Bits [31:8] of this register are Reserved. |
0xXXXX 0004 3 | RW |
0x407 | MAX_TX_SIZE_CONFIG | Specifies the maximum TX frame length. Frames that are longer are considered oversized. They are transmitted, but also increment the CNTR_TX_OVERSIZE register. Bits [31:16] of this register are Reserved. |
0xXXXX 2580 3 | RW |
0x40A | TX_MAC_CONTROL | TX MAC Control Register. A single bit is defined:
|
30'hX2'b0X 3 | RW |
3 X means "Don't Care".