AN 1013: Using Generic QSPI Flash on Control Block-Based Devices

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ID 855235
Date 6/30/2025
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Overview 3. Requirements 4. Implementation Flow 5. Programming Flow 6. QSPI Flash Examples 7. Document Revision History for AN 1013: Using Generic QSPI Flash on Control Block-Based Devices
3. Requirements x
3.1. I/O Standard Specification 3.2. Quad SPI Flash Byte Addressing 3.3. Disable Flash ID Check 3.4. Standard SPI Mode (1-1-1 Protocol) 3.5. Quad IO Mode (1-4-4 Protocol) 3.6. Sector Size 3.7. Maximum QSPI Clock Frequency 3.8. QSPI Read Opcode 3.9. Timing Specification
4. Implementation Flow x
4.1. Generating Programming Files Using the Convert Programming Files Feature 4.2. Programming .JIC Files into QSPI Flash Devices
5. Programming Flow x
5.1. Initialization Phase 5.2. Program Phase 5.3. Verify/Blank-Check/Examine Phase 5.4. Erase Phase 5.5. Termination
6. QSPI Flash Examples x
6.1. Cypress* S25HS512T with Cyclone® 10 GX 6.2. Macronix MX25L12833FMI-10G* with Cyclone® V
1. Introduction
2. Overview
3. Requirements
4. Implementation Flow
5. Programming Flow
6. QSPI Flash Examples
7. Document Revision History for AN 1013: Using Generic QSPI Flash on Control Block-Based Devices

6. QSPI Flash Examples

This section provides examples of QSPI flash devices with Altera FPGA devices for your reference.

In addition to the flash devices in the following examples, do refer to the Device Configuration – Support Center webpage for the full list of flash devices that are tested with Altera FPGA devices.


Section Content
Cypress* S25HS512T with Cyclone 10 GX
Macronix MX25L12833FMI-10G* with Cyclone V

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