AN 1013: Using Generic QSPI Flash on Control Block-Based Devices

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ID 855235
Date 6/30/2025
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Overview 3. Requirements 4. Implementation Flow 5. Programming Flow 6. QSPI Flash Examples 7. Document Revision History for AN 1013: Using Generic QSPI Flash on Control Block-Based Devices
3. Requirements x
3.1. I/O Standard Specification 3.2. Quad SPI Flash Byte Addressing 3.3. Disable Flash ID Check 3.4. Standard SPI Mode (1-1-1 Protocol) 3.5. Quad IO Mode (1-4-4 Protocol) 3.6. Sector Size 3.7. Maximum QSPI Clock Frequency 3.8. QSPI Read Opcode 3.9. Timing Specification
4. Implementation Flow x
4.1. Generating Programming Files Using the Convert Programming Files Feature 4.2. Programming .JIC Files into QSPI Flash Devices
5. Programming Flow x
5.1. Initialization Phase 5.2. Program Phase 5.3. Verify/Blank-Check/Examine Phase 5.4. Erase Phase 5.5. Termination
6. QSPI Flash Examples x
6.1. Cypress* S25HS512T with Cyclone® 10 GX 6.2. Macronix MX25L12833FMI-10G* with Cyclone® V
1. Introduction
2. Overview
3. Requirements
4. Implementation Flow
5. Programming Flow
6. QSPI Flash Examples
7. Document Revision History for AN 1013: Using Generic QSPI Flash on Control Block-Based Devices

3.9. Timing Specification

In the Active Serial configuration scheme, the FPGA initiates the configuration process after POR. During the configuration process, the FPGA issues flash operation commands such as read device ID, normal read, and sector erase.

As such, you must ensure that the FPGA is able to correctly read data from the configuration devices. This is done by ensuring the setup time, tDSU, and hold time, tDH, meets the requirements explained in the respective FPGA device datasheet.

Figure 6. FPGA to QSPI Board Trace Block Diagram

The FPGA device drives control signals on the falling edge of DCLK, and latches configuration data on the subsequent falling edge of DCLK. Dual and Quad SPI instructions use the bidirectional IO pins to serially write instructions, addresses, or data to the device on the rising edge of DCLK, and read data or status from the device on the falling edge of DCLK.

The data setup timing slack must be equal or larger than the minimum data setup time needed by FPGA, tDSU.

Therefore; tDCLK – (tBT_DCLK + tCLQV + tBT_DATA) ≥ tDSU

The data hold timing slack must be equal or larger than the minimum data hold time, tDH.

Therefore; tBT_DCLK + tCLQX + tBT_DATA ≥ tDH

Definitions:
  • tDCLK = Period for a DCLK cycle
  • tBT_DCLK = Board trace propagation delay for DCLK from FPGA to QSPI Flash
  • tCLQV = DCLK falling edge to DATA valid 1
  • tCLQX = Output hold time1
  • tBT_DATA = Board trace propagation delay for DATA from QSPI Flash to FPGA
  • tDSU = Minimum DATA setup time required by FPGA 2
  • tDH = Minimum DATA hold time required by FPGA2

Example: Calculating Valid Delay

Assuming the following for your system setup:
  1. DCLK frequency: 50 MHz (Period 20 ns)
  2. Cyclone® V AS timing specifications:
    • Minimum tDSU: 1.5 ns
    • Minimum tDH: 2.9 ns
  3. Altera EPCQ64ASI16N flash specifications:
    • tCLQV: 6 ns
    • tCLQX: 1.5 ns
Using the assumptions to identify the allowed maximum extra delay: 
tDCLK - (tBT_DCLK + tCLQV + tBT_DATAmax) ≥ tDSU
= (tBT_DCLK + tBT_DATAmax) ≤ tDCLK - tCLQV - tDSU
= (tBT_DCLK + tBT_DATAmax) ≤ 20 ns - 6 ns - 1.5 ns
= (tBT_DCLK + tBT_DATAmax) ≤ 12.5 ns

Therefore, the allowed maximum extra delay is 12.5 ns.

Using the assumptions to identify the allowed minimum extra delay: 
tBT_DCLK + tCLQX + tBT_DATAmin ≥ tDH
= tBT_DCLK + tBT_DATAmin ≥ tDH - tCLQX
= tBT_DCLK + tBT_DATAmin ≥ 2.9 ns - 1.5 ns
= tBT_DCLK + tBT_DATAmin ≥ 1.4 ns

Therefore, the allowed minimum extra delay is 1.4 ns.

In conclusion, the calculated range for extra delay is from 1.4 ns to 12.5 ns to meet the required FPGA data hold time, tDH, while not violating the data setup time specification, tDSU.

1 Refer to respective QSPI flash device datasheet on AC specification.
2 Refer to respective Altera FPGA device datasheet on Active Serial configuration specification.
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