AN 1013: Using Generic QSPI Flash on Control Block-Based Devices

Download PDF
ID 855235
Date 6/30/2025
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Overview 3. Requirements 4. Implementation Flow 5. Programming Flow 6. QSPI Flash Examples 7. Document Revision History for AN 1013: Using Generic QSPI Flash on Control Block-Based Devices
3. Requirements x
3.1. I/O Standard Specification 3.2. Quad SPI Flash Byte Addressing 3.3. Disable Flash ID Check 3.4. Standard SPI Mode (1-1-1 Protocol) 3.5. Quad IO Mode (1-4-4 Protocol) 3.6. Sector Size 3.7. Maximum QSPI Clock Frequency 3.8. QSPI Read Opcode 3.9. Timing Specification
4. Implementation Flow x
4.1. Generating Programming Files Using the Convert Programming Files Feature 4.2. Programming .JIC Files into QSPI Flash Devices
5. Programming Flow x
5.1. Initialization Phase 5.2. Program Phase 5.3. Verify/Blank-Check/Examine Phase 5.4. Erase Phase 5.5. Termination
6. QSPI Flash Examples x
6.1. Cypress* S25HS512T with Cyclone® 10 GX 6.2. Macronix MX25L12833FMI-10G* with Cyclone® V
1. Introduction
2. Overview
3. Requirements
4. Implementation Flow
5. Programming Flow
6. QSPI Flash Examples
7. Document Revision History for AN 1013: Using Generic QSPI Flash on Control Block-Based Devices

3.4. Standard SPI Mode (1-1-1 Protocol)

All QSPI flash devices support Standard SPI mode. Standard SPI mode is used during Active Serial x1 (ASx1) configuration.

The control block communicates with the QSPI flash device by sending opcode, address, and write data through data line 0 (ASDO-to-ASDI), and receiving read data and response from the flash device through data line 1 (DATA-to-AS_DATA1).

The following figure illustrates the signal lines used.
Figure 4. Standard SPI Mode
Level Two Title