While you can select various DCLK frequencies in your Quartus® Prime project, the supported DCLK frequencies have a dependency on your configuration clock source.
Make sure the DCLK frequency selected is less than the maximum supported QSPI clock frequency published in the respective QSPI flash device datasheet.
Refer to the following tables for supported DCLK frequencies depending on your control block-based FPGA device. Note that the internal oscillator’s frequencies shown in the tables are the maximum frequencies and vary depending on the device and operating conditions.
Table 4. Supported DCLK Frequencies in Cyclone® 10 LP DevicesFor Cyclone 10 LP devices, you must implement the JTAG instruction to change the configuration clock source to CLKUSR. For more information, refer to the Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook.
| Configuration Clock Source |
DCLK Frequency (MHz) |
| Internal Oscillator |
40 |
| CLKUSR |
Up to 40 |
Table 5. Supported DCLK Frequencies in Cyclone® 10 GX, Arria® 10, Arria® V, Cyclone® V, and Stratix® V Devices
| Configuration Clock Source |
DCLK Frequency (MHz) |
| Internal Oscillator |
12.5 |
| 25 |
| 50 |
| 100 |
| CLKUSR |
10 to 125 |
Table 6. Supported DCLK Frequencies in Cyclone® IV GX Devices
| Configuration Clock Source |
DCLK Frequency (MHz) |
| Internal Oscillator |
20 |
| 40 |
| CLKUSR |
Up to 40 |
Table 7. Supported DCLK Frequencies in Cyclone® IV E Devices
| Configuration Clock Source |
DCLK Frequency (MHz) |
| Internal Oscillator |
40 |