AN 1013: Using Generic QSPI Flash on Control Block-Based Devices

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ID 855235
Date 6/30/2025
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Overview 3. Requirements 4. Implementation Flow 5. Programming Flow 6. QSPI Flash Examples 7. Document Revision History for AN 1013: Using Generic QSPI Flash on Control Block-Based Devices
3. Requirements x
3.1. I/O Standard Specification 3.2. Quad SPI Flash Byte Addressing 3.3. Disable Flash ID Check 3.4. Standard SPI Mode (1-1-1 Protocol) 3.5. Quad IO Mode (1-4-4 Protocol) 3.6. Sector Size 3.7. Maximum QSPI Clock Frequency 3.8. QSPI Read Opcode 3.9. Timing Specification
4. Implementation Flow x
4.1. Generating Programming Files Using the Convert Programming Files Feature 4.2. Programming .JIC Files into QSPI Flash Devices
5. Programming Flow x
5.1. Initialization Phase 5.2. Program Phase 5.3. Verify/Blank-Check/Examine Phase 5.4. Erase Phase 5.5. Termination
6. QSPI Flash Examples x
6.1. Cypress* S25HS512T with Cyclone® 10 GX 6.2. Macronix MX25L12833FMI-10G* with Cyclone® V
1. Introduction
2. Overview
3. Requirements
4. Implementation Flow
5. Programming Flow
6. QSPI Flash Examples
7. Document Revision History for AN 1013: Using Generic QSPI Flash on Control Block-Based Devices

5.1. Initialization Phase

Overview of the Initialization Phase

The Initialization phase checks the flash ID and initializes the flash to a preferred non-volatile configuration (Config 1) at the beginning of flash programming. On the other hand, the Termination phase initializes the flash to a second non-volatile configuration (Config 2) at the end of flash programming.

  • In the event of no Termination phase, Config 1 is applied throughout the programming flows and during the Active Serial configuration after a power-on reset.
  • In the event of a valid Termination phase, Config 1 is applied throughout the programming flows. Upon the end of programming flow, Config 1 is reconfigured to Config 2. Thus, Config 2 is applied during the Active Serial configuration after a power-on reset.

To support Active Serial configuration, it is mandatory to apply flash configuration in compliance with stated requirements before programming flows end. Refer to the Requirements section for more information.

  • In the event of no Termination phase, this flash configuration must be carried out as Config 1 during the initialization phase.
  • In the event of a valid Termination phase, this flash configuration must be carried out as Config 2 during the Termination phase.
Table 8.  Flash Configuration Needed for Active Serial Configuration
Configuration Description Required
Byte Addressing Apply the same byte addressing during configuration.

Refer to the Quad SPI Byte Addressing section for more information.

Yes
Quad IO mode

When ASx4 is used, Quad IO mode must be enabled and QPI mode must be disabled.

It is recommended to enable Quad IO mode regardless of selected Active Serial configuration. Both ASx1 and ASx4 are supported during Quad IO mode.

Refer to the Quad IO Mode section for more information.

Yes
Uniform Sector Size Refer to the Sector Size section for more information. Yes
Altera recommends you implement the programming flow without the Termination phase. A simpler programming flow setup can be implemented by applying both programming and Active Serial under a single flash configuration.
Note: Volatile configuration reverts the flash back to default configuration, which may be incompatible with stated requirements. Refer to the Requirements section for more information.

The Initialization Phase Flow

Figure 11. Initialization Flow Template (Micron* Example)

Initialization begins with a Read ID action box. After sending a 9Fh (Read Flash ID) flash opcode, the Quartus® Prime Programmer expects 3 data bytes of QSPI Flash ID. You need to define the QSPI Flash ID in Expected data, and no data mask is required.

With flash configuration, every QSPI flash implements unique status and configuration registers to control its working state. In the example shown in the figure above, the Micron* flash implements three configuration registers (Non-Volatile Configuration Register, Volatile Configuration Register, and Enhanced Volatile Configuration Register). The initialization phase flow configures each configuration registers.

Any write operation from Quartus® Prime Programmer to these registers must be accompanied by a 06h (Write Enable) flash opcode. This is called a Write Enable & Write Register pair.

When writing to these registers, you need to provide the following information.

  • Command: The unique flash opcode to write the register.
  • Data: Bit field settings that define the new non-volatile flash configuration.
  • Delay (μs): Define 0, or a non-zero value when a minimum delay is specified in the AC specifications of the flash device datasheet.
Note: An alternative to using Delay (μs) is to poll the Write-In-Progress (WIP) bit from the Status Register using an RR action box. Quartus® Prime Programmer continues to the next action box after it receives an idle status from the WIP bit. Refer to the Erase Phase section for an example.

Depending on the Altera FPGA device, configure the QSPI flash device according to the Flash Configuration Needed for Active Serial Configuration table provided above. Some flash devices support dedicated flash opcode, such as the B7h (Set 4-byte addressing) flash command, as in the Micron* example. The same applies to Quad IO mode, and uniform sector size.

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