AN 1013: Using Generic QSPI Flash on Control Block-Based Devices

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ID 855235
Date 6/30/2025
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Overview 3. Requirements 4. Implementation Flow 5. Programming Flow 6. QSPI Flash Examples 7. Document Revision History for AN 1013: Using Generic QSPI Flash on Control Block-Based Devices
3. Requirements x
3.1. I/O Standard Specification 3.2. Quad SPI Flash Byte Addressing 3.3. Disable Flash ID Check 3.4. Standard SPI Mode (1-1-1 Protocol) 3.5. Quad IO Mode (1-4-4 Protocol) 3.6. Sector Size 3.7. Maximum QSPI Clock Frequency 3.8. QSPI Read Opcode 3.9. Timing Specification
4. Implementation Flow x
4.1. Generating Programming Files Using the Convert Programming Files Feature 4.2. Programming .JIC Files into QSPI Flash Devices
5. Programming Flow x
5.1. Initialization Phase 5.2. Program Phase 5.3. Verify/Blank-Check/Examine Phase 5.4. Erase Phase 5.5. Termination
6. QSPI Flash Examples x
6.1. Cypress* S25HS512T with Cyclone® 10 GX 6.2. Macronix MX25L12833FMI-10G* with Cyclone® V
1. Introduction
2. Overview
3. Requirements
4. Implementation Flow
5. Programming Flow
6. QSPI Flash Examples
7. Document Revision History for AN 1013: Using Generic QSPI Flash on Control Block-Based Devices

6.2. Macronix MX25L12833FMI-10G* with Cyclone® V

Table 12.  Macronix MX25L12833FMI-10G with Cyclone® V Requirements
Item FPGA Requires? Flash Provides?
I/O Voltage 3.3 V 3.3 V
Byte Addressing 3-byte 3-byte
Disable Flash ID Check – Yes
Standard SPI Mode Yes Yes
Quad IO Mode Yes Yes
Sector Size – Uniform 64 KB
QSPI Read Opcode
  • 0Bh for ASx1
  • EBh for ASx4
 0Bh and EBh

In Convert Programming File, select the MX25L128 as Configuration Device. The device parameters and programming flow are readily available in the Quartus® Prime software. You are not required to create a new MX25L128 option.

Figure 16. MX25L128 Device Configuration
Level Two Title