AN 1013: Using Generic QSPI Flash on Control Block-Based Devices

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ID 855235
Date 6/30/2025
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Overview 3. Requirements 4. Implementation Flow 5. Programming Flow 6. QSPI Flash Examples 7. Document Revision History for AN 1013: Using Generic QSPI Flash on Control Block-Based Devices
3. Requirements x
3.1. I/O Standard Specification 3.2. Quad SPI Flash Byte Addressing 3.3. Disable Flash ID Check 3.4. Standard SPI Mode (1-1-1 Protocol) 3.5. Quad IO Mode (1-4-4 Protocol) 3.6. Sector Size 3.7. Maximum QSPI Clock Frequency 3.8. QSPI Read Opcode 3.9. Timing Specification
4. Implementation Flow x
4.1. Generating Programming Files Using the Convert Programming Files Feature 4.2. Programming .JIC Files into QSPI Flash Devices
5. Programming Flow x
5.1. Initialization Phase 5.2. Program Phase 5.3. Verify/Blank-Check/Examine Phase 5.4. Erase Phase 5.5. Termination
6. QSPI Flash Examples x
6.1. Cypress* S25HS512T with Cyclone® 10 GX 6.2. Macronix MX25L12833FMI-10G* with Cyclone® V
1. Introduction
2. Overview
3. Requirements
4. Implementation Flow
5. Programming Flow
6. QSPI Flash Examples
7. Document Revision History for AN 1013: Using Generic QSPI Flash on Control Block-Based Devices

2. Overview

During Active Serial configuration, control block-based FPGA devices uses the control block to interact with the QSPI flash devices through the QSPI controller that is part of the FPGA hardware inside the chip.

The following figure illustrates a simple block diagram of the control block and the QSPI flash device.

Figure 1. Control Block Connection to QSPI Controller and QSPI Flash Device

Active Serial Configuration Sequence

Upon device power up, the control block samples the Mode Select (MSEL) pins setting. When the control block identifies the QSPI as the bitstream source, the control block drives the nSTATUS high and the DCLK pin with the default 12.5 MHz internal oscillator to read the configuration bitstream from the serial flash.

Next, the control block checks the QSPI flash ID for EPCS or EPCQ devices. When used with third-party QSPI flash devices, the flash device ID check must be disabled.

After that, the control block determines the configuration options such as clock source frequency and Active Serial scheme (ASx1 or ASx4), by reading the option bits, located from 0x80 to 0x127, at the start of the programming file stored in the serial flash.

After the option bit is decoded by the control block, the FPGA device switches to the new clock source (frequency) and AS mode based on the option bits. The AS configuration continues by reading the rest of the programming file from the serial flash until the CONF_DONE pin asserts high and eventually enters user mode.

Should any interruption (such as data corruption) occur in the middle of the AS configuration, the nSTATUS pin asserts low to indicate a configuration error, and deasserts high to restart the configuration process. If there is no image in the serial flash or if the image is corrupted, the nSTATUS pulses low repeatedly as the control block tries to configure itself until the configuration is successful.

The following diagram illustrates the sequence.

Figure 2. Active Serial Configuration Sequence

By familiarizing yourself with the above Active Serial configuration process, you can better understand how to identify a QSPI flash that meets the necessary flash specifications, as provided in the Requirements section.

You can generate and program the programming file to the QSPI flash device, using the Quartus® Prime Programmer, or a third-party programmer.

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