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13. [HL-NO-DDR] Quartus® Prime System Console
This design example requires user interaction on the host system through Quartus® Prime System Console. For more information about the Quartus® Prime System Console, refer to "Analyzing and Debugging Designs with System Console" in Quartus® Prime Pro Edition User Guide: Debug Tools .
- Read/write to the FPGA AI Suite IP DMA CSR
For more information about the FPGA AI Suite IP CSR map, refer to "CSR Map and Descriptor Queue" in the FPGA AI Suite IP Reference Manual
- Read/write to ingress and egress on-chip memory
- Read/write to ingress and egress modular scatter-gather DMA (mSGDMA) CSR
For more information about mSGDMA CSR, refer to "Register Map of mSGDMA" in Embedded Peripherals IP User Guide .
$COREDLA_ROOT/runtime/streaming/ed0_streaming_example/system_console_script.tcl
Use this only functional testing in hardware. For performance testing, refer to the script described in [HL-NO-DDR] Quartus Prime System Console Performance Script.