FPGA AI Suite: Design Examples User Guide

ID 848957
Date 4/22/2025
Public

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12.2.3. [HL-NO-DDR] Platform Designer System

The on-chip memory modules, mSGDMA engines, and other components are instantiated and interconnected within the board.qsys Platform Designer system. This comprehensive system design is then instantiated as an IP block within the top.sv file, ensuring seamless integration and efficient operation of the entire design.