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2. FPGA AI Suite Design Examples
The FPGA AI Suite Design Examples User Guide provides information about the following design examples.
Design Example | Description | Symbol |
---|---|---|
PCIe-based design example | Demonstrates how OpenVINO™ toolkit and the FPGA AI Suite support the look-aside deep learning acceleration model. This design example targets the Terasic* DE10-Agilex Development Board (DE10-Agilex-B2E2). |
[PCIE] |
OFS PCIe-attach design example | Demonstrates the OpenVINO™ toolkit and the FPGA AI Suite that target Open FPGA Stack (OFS)-based boards.
This design example targets the following Open FPGA Stack (OFS)-based boards:
|
[OFS-PCIE] |
Hostless DDR-Free design examples | Demonstrates hostless DDR-free operation of the FPGA AI Suite IP. Graph filters, bias, and FPGA AI Suite IP configurations are stored in internal memory on the FPGA device. This design example targets the Agilex™ 7 FPGA I-Series Development Kit ES2 (DK-DEV-AGI027RBES). |
[HL-NO-DDR] |
Hostless JTAG design example | Demonstrates the step-by-step sequence of configuring FPGA AI Suite IP and starting inference by writing into CSRs directly via JTAG. This design example targets the Agilex™ 5 FPGA E-Series 065B Premium Development Kit (DK-A5E065BB32AES1). |
[HL-JTAG] |
SoC design example | Demonstrates how OpenVINO™ toolkit and the FPGA AI Suite support the CPU-offload deep-learning acceleration model in an embedded system.
The design example targets the following development boards:
|
[SOC] |
Example Design Type | Target FPGA Device | Host | Memory | Stream* | Identifier | Supported Development Kit |
---|---|---|---|---|---|---|
PCIe Attached | Agilex™ 7 | External host processor | DDR | M2M | agx7_de10_pcie | Terasic* DE10-Agilex Development Board (DE10-Agilex-B2E2) |
agx7_iseries_ofs_pcie | Agilex™ 7 FPGA I-Series Development Kit ES2 (DK-DEV-AGI027RBES) | |||||
agx7_n6001_ofs_pcie | Intel® FPGA SmartNIC N6001-PL Platform (without Ethernet controller) | |||||
Hostless DDR-Free | Agilex™ 7 | Hostless | DDR-Free | Direct | agx7_iseries_ddrfree | Agilex™ 7 FPGA I-Series Development Kit ES2 (DK-DEV-AGI027RBES) |
Hostless JTAG-Attach | Agilex™ 5 | DDR | M2M | agx5e_modular_Jtag | Agilex™ 5 FPGA E-Series 065B Premium Development Kit (DK-A5E065BB32AES1) | |
SoC | Agilex™ 7 | On-device HPS | DDR | M2M and S2M |
agx7_soc_m2m agx7_soc_s2m |
Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit (DK-SI-AGI027FC) |
Arria® 10 | a10_soc_m2m a10_soc_s2m |
Arria® 10 SX SoC FPGA Development Kit (DK-SOC-10AS066S) |