FPGA AI Suite: Design Examples User Guide

ID 848957
Date 4/22/2025
Public

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13.1. [HL-NO-DDR] Functionality

The process of executing an inference on the DDR-Free design example involves the following steps in the Quartus® Prime System Console. Each step translates to a specific Tcl process in the system_console_script.tcl script:
  1. Prime the FPGA AI Suite IP’s CSR and resets the SGDMA’s for streaming inference.
    initialize_coredla{}
  2. Load raw input features into ingress on-chip memory
    stage_input{}
  3. Queue a descriptor into the ingress SGDMA for MM to streaming operation
    queue_ingress_descriptor{}
  4. Queue a descriptor into the egress SGDMA for streaming to MM operation
    queue_egress_descriptor{}
  5. Reads inference results from the egress on-chip memory
    read_output{}