FPGA AI Suite: Design Examples User Guide

ID 848957
Date 4/22/2025
Public

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Document Table of Contents

2.1. About the PCIe* -Based Design Example

The FPGA AI Suite PCIe* -based design example demonstrates how the Intel® Distribution of OpenVINO™ toolkit and the FPGA AI Suite support the look-aside deep learning acceleration model.

The PCIe-based design example is implemented with the following components:

  • FPGA AI Suite IP
  • Intel® Distribution of OpenVINO™ toolkit
  • Terasic* DE10-Agilex Development Board
  • Sample hardware and software systems that illustrate the use of these components

This design example includes pre-built FPGA bitstreams that correspond to pre-optimized architecture files. However, the design example build scripts let you choose from a variety of architecture files and build (or rebuild) your own bitstreams, provided that you have a license permitting bitstream generation.

This design is provided with the FPGA AI Suite as an example showing how to incorporate the IP into a design. This design is not intended for unaltered use in production scenarios. Any potential production application that uses portions of this example design must review them for both robustness and security.

The following sections in this document describe the steps to build and execute the design:
The following sections in this document describe design decisions and architectural details about the design:

Use this document to help you understand how to create a PCIe example design with the targeted FPGA AI Suite architecture and number of instances and compiling the design for use with the Intel FPGA Basic Building Blocks (BBBs) system.