FPGA AI Suite: Design Examples User Guide

ID 848957
Date 4/22/2025
Public

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Document Table of Contents

12.1. [HL-NO-DDR] System Overview

The FPGA image consists of the FPGA AI Suite IP and additional logic that connects the IP to a JTAG interface. The DDR-Free design example does not use the dla_benchmark runtime. Instead, it allows for communication and control of the FPGA AI Suite IP through a JTAG- Quartus® Prime System Console connection. In addition, the DDR-Free design example showcases the FPGA AI Suite IP streaming functionality. For more information about feature input and output streaming, refer to "Feature Input and Output Streaming" in FPGA AI Suite IP Reference Manual .

The system configuration of this design example is shown in the following block diagram:
Figure 6. DDR-Free Design Example System Configuration