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8.2.4. [OFS-PCIE] Compiling the OFS for PCIe* Attach Design Example
To build example design bitstreams, you must have a license that permits bitstream generation for the IP, and have the correct version of Quartus® Prime software installed. Use the dla_build_example_design.py utility to create a bitstream.
For more details about this command, the steps it performs, and advanced command options, refer to Build Script and to the FPGA AI Suite Getting Started Guide .
https://github.com/OFS/ofs-agx7-pcie-attach/releases/The FPGA AI Suite OFS for PCIe* Attach design example is based on the OFS 2024.2-1 release of the reference shells.
The dla_build_example_design.py utility generates a wrapper that wraps one or more FPGA AI Suite IP instances along with adapters required to connect to the OFS slim FIM.
Get an estimate of the FPGA resource required for a single FPGA AI Suite IP instance by using the --fanalyze-area option of the dla_compiler. Use the single instance values to determine the resources required for the number of instances that you want. For more details, see the --fanalyze-area option description in FPGA AI Suite Compiler Reference Manual .
Option | Description |
---|---|
-a, --archs | Path to FPGA AI Suite IP Architecture Description File |
--build-dir | Path to hardware build directory where BSP infrastructure and generated RTL will be located. |
--build | Option to perform compilation of the design using Quartus® Prime after instantiation (default: False). |
-d, --archs-dir | Path to directory that contains Architecture Description Files for you to interactively choose from (alternative to ‘-a’) |
-ed, --example-design-id | To build for the Agilex™ 7 FPGA I-Series Development Kit, specify AGX7_ISERIES_OFS_PCIE. To build for the Intel® FPGA SmartNIC N6001-PL Platform, specify AGX7_N6001_OFS_PCIE. |
-n, --num-instances | Number of IP instances to build (default: 2). To build for the Agilex™ 7 FPGA I-Series Development Kit, this value can be 1, 2, 3, or 4. To build for the Intel® FPGA SmartNIC N6001-PL Platform, this value can be 1 or 2. |
--num-paths | Number of top critical paths to report after compiling the design (default: 2000). |
-q, --quiet | Run script quietly without printing the output of underlying scripts to the terminal. |
-qor-modules | List of internal modules (instance names) from inside the FPGA AI Suite IP to include in the QoR summary report. |
-s, --seed | Quartus® Prime fitter initial placement seed to use when compiling the design (default: 1). |
--unlicensed/licensed |
This option is passed to the dla_create_ip tool to tell the tool to generate either an unlicensed or licensed copy of the FPGA AI Suite IP:
If you do not have a license but generate licensed IP, Quartus® Primesoftware cannot generate a bitstream. If neither option is specified, then the dla_create_ip tool queries the lmutil license manager to determine the correct option. |
cd $COREDLA_WORK $COREDLA_ROOT/bin/dla_build_example_design.py \ -n 2 \ --archs=$COREDLA_ROOT/example_architectures/AGX7_Generic.arch \ --build \ --build-dir=build_generic_2inst \ --example-design-id="AGX7_ISERIES_OFS_PCIE" \ --seed=1
This command generates a green bitstream (GBS) file called AGX7_Generic.gbs that can be found in the $COREDLA_WORK/build_generics_2inst/ folder.