FPGA AI Suite: Design Examples User Guide

ID 848957
Date 4/22/2025
Public

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22.6. [SOC] Fabric EMIF Design Component

The design provides a 266MHz DDR4-64Bit Avalon® -based memory controller. This EMIF is used solely by the DLA.

The FPGA AI Suite IP memory interface is configured to be 512 bits wide. The EMIF interface is setup to complement this configuration.