AN 1016: Timing Closure Methodology Quick Reference Guide

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ID 836192
Date 11/15/2024
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. About This Application Note 2. RTL Analysis and Optimization Techniques 3. Post-Fit Analysis and Optimization Techniques 4. Additional Optimization Techniques 5. Iterative Analysis and Optimization 6. Document Revision History of AN 1016: Timing Closure Methodology Quick Reference Guide
2. RTL Analysis and Optimization Techniques x
2.1. Optimization Before Synthesis 2.2. Optimization After Analysis & Elaboration 2.3. Analysis After Synthesis
2.2. Optimization After Analysis & Elaboration x
2.2.1. Check Design Rules with Design Assistant 2.2.2. Preview the Design in RTL Analyzer
2.3. Analysis After Synthesis x
2.3.1. Reduce Excessive Logic Levels 2.3.2. Evaluate SDC-on-RTL Constraints 2.3.3. Verify Memory Resources 2.3.4. Confirm State Machine Recognition
3. Post-Fit Analysis and Optimization Techniques x
3.1. Define Post-Fit Timing Constraints 3.2. Analyze Post-Fit Timing Analysis Results
3.2. Analyze Post-Fit Timing Analysis Results x
3.2.1. Analyze Post-Fit Timing Reports 3.2.2. Cross-Probe with Design Assistant 3.2.3. Analyze Fitter Reports 3.2.4. Reduce Register-to-Register Delays
3.2.3. Analyze Fitter Reports x
3.2.3.1. Review RAM and DSP Reports 3.2.3.2. View Resource Usage and Congestion Reports
3.2.4. Reduce Register-to-Register Delays x
3.2.4.1. Report Logic Depth 3.2.4.2. Manually Duplicate Logic 3.2.4.3. Optimize Shift Registers
4. Additional Optimization Techniques x
4.1. Use the Fast Forward Compilation Flow 4.2. Apply Compiler Optimization Settings 4.3. Optimize the Design Floorplan 4.4. Run Design Space Explorer II 4.5. Run Exploration Dashboard 4.6. Back-Annotate Assignments
4.1. Use the Fast Forward Compilation Flow x
4.1.1. Facilitate Register Movement
Answers to Top FAQs
1. About This Application Note
2. RTL Analysis and Optimization Techniques
3. Post-Fit Analysis and Optimization Techniques
4. Additional Optimization Techniques
5. Iterative Analysis and Optimization
6. Document Revision History of AN 1016: Timing Closure Methodology Quick Reference Guide

3.2.3.2. View Resource Usage and Congestion Reports

Excessive utilization of interconnect resources within a design can often lead to timing challenges. The Average Interconnect Usage timing data represents the average amount of interconnect utilized, compared with available resources on the device. When this value exceeds 65%, this may indicate difficulties in meeting timing requirements. Similarly, the Peak Interconnect Usage reports the maximum utilization in the most congested regions. When this value reaches or surpasses 90%, this may indicate potential timing closure issues. A peak value of 100% signifies complete routing saturation in a specific device area, significantly increasing the possibility of timing degradation. You can access average and peak interconnect usage metrics in the Fitter Resource Usage Summary report.

Figure 15. Fitter Resource Usage Summary


To assess congestion, consult the Global Router Congestion Hotspot Summary Report and the Global Router Wire Utilization Map, accessible from the Route Stage Reports in the Compilation Report.

The Global Router Congestion Hotspot Summary report identifies congested net hotspots within the design using a hierarchical node name. This report presents the ratio defined by the number of nets under the current hierarchical level that overlap with the largest group of adjacent grids whose short wire usage exceeds capacity, divided by the total number of nets under the current hierarchical level.

Figure 16. Global Router Congestion Hotspot Summary Report


The Global Router Wire Utilization Map visually represents the Global Router Congestion Hotspot Summary Report, presenting global signal routing via an interactive heatmap. This map illustrates the routing utilization rate of both long and short routing wires, offering a detailed view of all nets in the design. The heatmap grid corresponds to the LABs available in the device, with colors ranging from blue to red, indicating utilization rates from 0% to 100%. The pink color denotes utilization rates exceeding 100%.

Figure 17. Global Router Wire Utilization Map


You can select any Instance from the list to see more details about that instance's utilization.

Figure 18. Details of Instance Utilization


Additionally, the Chip Planner provides a comprehensive visual overview of congested areas through the Report Routing Utilization task. This report presents precise percentages of routing utilization across different utilization types in the current compilation. Through a configurable color scale, the report offers a clear representation of congestion levels. For guidance on configuring the Report Routing Utilization task, please refer to Viewing Routing Congestion in Chip Planner in Quartus Prime Pro Edition User Guide: Design Optimization.

Figure 19. Report Routing Utilization Report


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