AN 1016: Timing Closure Methodology Quick Reference Guide

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ID 836192
Date 11/15/2024
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. About This Application Note 2. RTL Analysis and Optimization Techniques 3. Post-Fit Analysis and Optimization Techniques 4. Additional Optimization Techniques 5. Iterative Analysis and Optimization 6. Document Revision History of AN 1016: Timing Closure Methodology Quick Reference Guide
2. RTL Analysis and Optimization Techniques x
2.1. Optimization Before Synthesis 2.2. Optimization After Analysis & Elaboration 2.3. Analysis After Synthesis
2.2. Optimization After Analysis & Elaboration x
2.2.1. Check Design Rules with Design Assistant 2.2.2. Preview the Design in RTL Analyzer
2.3. Analysis After Synthesis x
2.3.1. Reduce Excessive Logic Levels 2.3.2. Evaluate SDC-on-RTL Constraints 2.3.3. Verify Memory Resources 2.3.4. Confirm State Machine Recognition
3. Post-Fit Analysis and Optimization Techniques x
3.1. Define Post-Fit Timing Constraints 3.2. Analyze Post-Fit Timing Analysis Results
3.2. Analyze Post-Fit Timing Analysis Results x
3.2.1. Analyze Post-Fit Timing Reports 3.2.2. Cross-Probe with Design Assistant 3.2.3. Analyze Fitter Reports 3.2.4. Reduce Register-to-Register Delays
3.2.3. Analyze Fitter Reports x
3.2.3.1. Review RAM and DSP Reports 3.2.3.2. View Resource Usage and Congestion Reports
3.2.4. Reduce Register-to-Register Delays x
3.2.4.1. Report Logic Depth 3.2.4.2. Manually Duplicate Logic 3.2.4.3. Optimize Shift Registers
4. Additional Optimization Techniques x
4.1. Use the Fast Forward Compilation Flow 4.2. Apply Compiler Optimization Settings 4.3. Optimize the Design Floorplan 4.4. Run Design Space Explorer II 4.5. Run Exploration Dashboard 4.6. Back-Annotate Assignments
4.1. Use the Fast Forward Compilation Flow x
4.1.1. Facilitate Register Movement
Answers to Top FAQs
1. About This Application Note
2. RTL Analysis and Optimization Techniques
3. Post-Fit Analysis and Optimization Techniques
4. Additional Optimization Techniques
5. Iterative Analysis and Optimization
6. Document Revision History of AN 1016: Timing Closure Methodology Quick Reference Guide

4.1. Use the Fast Forward Compilation Flow

The Hyperflex® architecture of Stratix® 10 and Agilex™ 7 devices features multiple Hyper-Registers in every routing segment and block input. Maximizing the use of Hyper-Registers balances the time delay between registers and mitigates critical path delays. After place and route, the Fitter runs the Retime stage to enhance performance by relocating registers from ALMs into Hyper-Registers. The Retiming Limit Details report, accessible from the Retime Stage folder in the Compilation Report, lists the number of registers moved, their paths, and the limiting reasons preventing further retiming.

Figure 24. Retiming Limit Details Report


The Fast Forward Compilation Report provides design recommendations to alleviate performance bottlenecks and maximize Hyper-Register utilization for optimal performance. This report predicts the maximum performance achievable after removing retiming restrictions. The Fast Forward Compilation Report details the current maximum frequency and potential performance for each clock domain, including various optimization steps starting from the pre-optimization base compilation. Each step includes its associated critical chain and represents a new optimization layer, suggesting modifications to your RTL to facilitate Hyper-Register movement.

Figure 25. Fast Forward Details for Clock Domain


Prioritize the recommendations that offer the most significant benefits, then recompile the design to achieve the performance levels reported in the Fast Forward Report. To delve deeper into the use of the Fast Forward Timing Closure Recommendations, refer to Implement Fast Forward Timing Closure Recommendations in the Quartus Prime Pro Edition User Guide: Design Optimization, and the Fast Forward Compilation Flow in the Quartus Prime Pro Edition User Guide: Design Compilation.


Section Content
Facilitate Register Movement

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