AN 1016: Timing Closure Methodology Quick Reference Guide
3.1. Define Post-Fit Timing Constraints
Properly defining timing constraints is a crucial step in the FPGA design process. Defining timing constraints after running the Fitter allows you to complement or override the constraints defined during the Analysis & Synthesis stage via SDC-on-RTL. You can achieve this by manually specifying parameters such as clock definitions, input and output delays, and clock domains, or by defining additional constraints that rely on Altera IP. Running the Fitter is necessary before constraining nodes or modules that depend on Altera IP definitions, such as clocks defined within these IP. These constraints act as directives that guide the Fitter in achieving optimal performance, while avoiding issues like setup and hold violations, clock skew, and excessive delays.
The Timing Analyzer relies on your constraints to analyze paths within the design. If you omit any critical constraints, the Timing Analyzer does not report on these constraints and may generate reports that mask potential issues. Additionally, a well-defined timing constraint set facilitates practical design analysis, debugging, and optimization throughout the design cycle. For more information about creating timing constraints and exceptions, refer to Recommended Initial Conventional SDC Constraints in the Quartus Prime Pro Edition User Guide: Timing Analyzer.
The Quartus Prime Timing Analyzer is a versatile tool that generates diagnostic reports to validate your specified timing constraints effectively. These reports provide the details about each timing constraint that you apply during the Fitter or earlier compilation stages. The Timing Analyzer identifies defined clocks, input and output delays, timing exceptions, and unconstrained paths, among other crucial metrics. Moreover, the timing reports detail the scope of each constraint that you set, distinguishing between fully or partially applied constraints, such as entity bounded timing constraints, that you can employ to target only specific modules within the design. For more information about the diagnostic reports the Timing Analyzer generates, refer to Check Constraint Diagnostics in the AN 584: Timing Closure Methodology for Advanced FPGA Designs and to Applying Timing Constraints in the Quartus Prime Pro Edition User Guide: Timing Analyzer.