AN 1016: Timing Closure Methodology Quick Reference Guide

ID 836192
Date 11/15/2024
Public
Document Table of Contents

3.2.4.1. Report Logic Depth

To report paths with high logic levels, follow these steps after running the Fitter:

  1. In the Timing Analyzer, click Task > Report > Design Metrics > Report Logic Depth. Generate this report for each clock domain.
  2. For paths with high logic levels, consider restructuring these paths by recoding the RTL or by using retiming techniques.
Figure 20. Report Logic Depth Report