AN 1016: Timing Closure Methodology Quick Reference Guide
ID
836192
Date
11/15/2024
Public
Answers to Top FAQs
1. About This Application Note
2. RTL Analysis and Optimization Techniques
3. Post-Fit Analysis and Optimization Techniques
4. Additional Optimization Techniques
5. Iterative Analysis and Optimization
6. Document Revision History of AN 1016: Timing Closure Methodology Quick Reference Guide
3.2.4.1. Report Logic Depth
To report paths with high logic levels, follow these steps after running the Fitter:
- In the Timing Analyzer, click Task > Report > Design Metrics > Report Logic Depth. Generate this report for each clock domain.
- For paths with high logic levels, consider restructuring these paths by recoding the RTL or by using retiming techniques.
Figure 20. Report Logic Depth Report