AN 1016: Timing Closure Methodology Quick Reference Guide

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ID 836192
Date 11/15/2024
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. About This Application Note 2. RTL Analysis and Optimization Techniques 3. Post-Fit Analysis and Optimization Techniques 4. Additional Optimization Techniques 5. Iterative Analysis and Optimization 6. Document Revision History of AN 1016: Timing Closure Methodology Quick Reference Guide
2. RTL Analysis and Optimization Techniques x
2.1. Optimization Before Synthesis 2.2. Optimization After Analysis & Elaboration 2.3. Analysis After Synthesis
2.2. Optimization After Analysis & Elaboration x
2.2.1. Check Design Rules with Design Assistant 2.2.2. Preview the Design in RTL Analyzer
2.3. Analysis After Synthesis x
2.3.1. Reduce Excessive Logic Levels 2.3.2. Evaluate SDC-on-RTL Constraints 2.3.3. Verify Memory Resources 2.3.4. Confirm State Machine Recognition
3. Post-Fit Analysis and Optimization Techniques x
3.1. Define Post-Fit Timing Constraints 3.2. Analyze Post-Fit Timing Analysis Results
3.2. Analyze Post-Fit Timing Analysis Results x
3.2.1. Analyze Post-Fit Timing Reports 3.2.2. Cross-Probe with Design Assistant 3.2.3. Analyze Fitter Reports 3.2.4. Reduce Register-to-Register Delays
3.2.3. Analyze Fitter Reports x
3.2.3.1. Review RAM and DSP Reports 3.2.3.2. View Resource Usage and Congestion Reports
3.2.4. Reduce Register-to-Register Delays x
3.2.4.1. Report Logic Depth 3.2.4.2. Manually Duplicate Logic 3.2.4.3. Optimize Shift Registers
4. Additional Optimization Techniques x
4.1. Use the Fast Forward Compilation Flow 4.2. Apply Compiler Optimization Settings 4.3. Optimize the Design Floorplan 4.4. Run Design Space Explorer II 4.5. Run Exploration Dashboard 4.6. Back-Annotate Assignments
4.1. Use the Fast Forward Compilation Flow x
4.1.1. Facilitate Register Movement
Answers to Top FAQs
1. About This Application Note
2. RTL Analysis and Optimization Techniques
3. Post-Fit Analysis and Optimization Techniques
4. Additional Optimization Techniques
5. Iterative Analysis and Optimization
6. Document Revision History of AN 1016: Timing Closure Methodology Quick Reference Guide

3.2.2. Cross-Probe with Design Assistant

The Design Assistant automatically identifies violations against a set of predefined design rules during all compilation stages. When you access Design Assistant from the Timing Analyzer, Design Assistant performs design rule checks using the latest compilation snapshot data.

The Design Assistant detects any rule violations and assists in resolving them by providing recommendations for corrections and pathways to the source of the violation. In addition, Design Assistant also provides the flexibility to select specific rules for execution at different compilation stages, streamlining the design closure process. For a practical demonstration of utilizing the Design Assistant to fix SDC and clock domain crossing issues within a design, refer to AN 919: Improving Quality Results with Design Assistant.

Follow these steps to run the Design Assistant from the Timing Analyzer:

  1. Compile the design through at least the Plan stage.
  2. In the Compilation Dashboard, click the Timing Analyzer icon for the completed Compiler stage. The Timing Analyzer opens.
  3. In the Timing Analyzer, click Reports > Design Assistant > Report DRC. The Report DRC (design rule checks) dialog box opens.
    Figure 11. Report DRC Dialog Box


  4. Under Rules, disable any rules that are not important to your analysis by removing the check mark.
  5. Consider whether to adjust rule parameter values in the Parameters field.
  6. Confirm the Report panel name and optionally specify an output File name.
  7. Click OK. The Results reports generate and appear in the Report pane and the main Compilation Report.
Figure 12. Rules Reported in Design Assistant Window


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