AN 1016: Timing Closure Methodology Quick Reference Guide

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ID 836192
Date 11/15/2024
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. About This Application Note 2. RTL Analysis and Optimization Techniques 3. Post-Fit Analysis and Optimization Techniques 4. Additional Optimization Techniques 5. Iterative Analysis and Optimization 6. Document Revision History of AN 1016: Timing Closure Methodology Quick Reference Guide
2. RTL Analysis and Optimization Techniques x
2.1. Optimization Before Synthesis 2.2. Optimization After Analysis & Elaboration 2.3. Analysis After Synthesis
2.2. Optimization After Analysis & Elaboration x
2.2.1. Check Design Rules with Design Assistant 2.2.2. Preview the Design in RTL Analyzer
2.3. Analysis After Synthesis x
2.3.1. Reduce Excessive Logic Levels 2.3.2. Evaluate SDC-on-RTL Constraints 2.3.3. Verify Memory Resources 2.3.4. Confirm State Machine Recognition
3. Post-Fit Analysis and Optimization Techniques x
3.1. Define Post-Fit Timing Constraints 3.2. Analyze Post-Fit Timing Analysis Results
3.2. Analyze Post-Fit Timing Analysis Results x
3.2.1. Analyze Post-Fit Timing Reports 3.2.2. Cross-Probe with Design Assistant 3.2.3. Analyze Fitter Reports 3.2.4. Reduce Register-to-Register Delays
3.2.3. Analyze Fitter Reports x
3.2.3.1. Review RAM and DSP Reports 3.2.3.2. View Resource Usage and Congestion Reports
3.2.4. Reduce Register-to-Register Delays x
3.2.4.1. Report Logic Depth 3.2.4.2. Manually Duplicate Logic 3.2.4.3. Optimize Shift Registers
4. Additional Optimization Techniques x
4.1. Use the Fast Forward Compilation Flow 4.2. Apply Compiler Optimization Settings 4.3. Optimize the Design Floorplan 4.4. Run Design Space Explorer II 4.5. Run Exploration Dashboard 4.6. Back-Annotate Assignments
4.1. Use the Fast Forward Compilation Flow x
4.1.1. Facilitate Register Movement
Answers to Top FAQs
1. About This Application Note
2. RTL Analysis and Optimization Techniques
3. Post-Fit Analysis and Optimization Techniques
4. Additional Optimization Techniques
5. Iterative Analysis and Optimization
6. Document Revision History of AN 1016: Timing Closure Methodology Quick Reference Guide

4.4. Run Design Space Explorer II

During the Fitter stage of compilation, the Compiler starts the place and route process by assigning an initial, semi-random placement to the logic elements. This starting point is determined by the Fitter Seed. The Fitter Seed is a numeric value influenced by a variety of factors, such as design characteristics, Compiler settings, the nature of the source files, and value of the Fitter Initial Placement Seed parameter. Any modifications to the project settings, source files, net or pin names, or new assignments result in a different Fitter Seed, which in turn can result in significantly different place and route results.

By adjusting the Fitter Seed, which is a non-negative integer, you can experiment with various initial placements without the need to alter the actual design or its settings. This approach allows the Compiler to start from a different set of conditions for each compilation, thereby avoiding repetitive obstacles that can arise during multiple compilations. Such a strategy can be particularly effective for addressing minor timing closure issues, potentially eliminating the need for extensive additional analysis. For guidance on manipulating the input Fitter seed, refer to Change Fitter Placement Seeds in AN 584: Timing Closure for Advanced FPGA Designs.

You can use the Design Space Explorer II to help you determine the optimal project settings to achieve specific resource, performance, or power optimization objectives. Design Space Explorer II is especially effective addressing marginal timing issues, where slight variations during placement and routing can impact adherence to timing constraints. This approach systematically processes a design through various combinations of settings and constraints to find the most effective configuration.

You specify your optimization preferences for Design Space Explorer II seed sweeps in the Settings tab. A seed sweep allows for easy access to detailed reports and data on resource utilization, timing analysis, and other relevant details for each point of exploration.

Access the Design Space Explorer II in the Quartus Prime software by clicking Tools > Design Space Explorer II. For a more thorough understanding, consider learning more with the Using Design Space Explorer II training.

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