AN 1016: Timing Closure Methodology Quick Reference Guide

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ID 836192
Date 11/15/2024
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. About This Application Note 2. RTL Analysis and Optimization Techniques 3. Post-Fit Analysis and Optimization Techniques 4. Additional Optimization Techniques 5. Iterative Analysis and Optimization 6. Document Revision History of AN 1016: Timing Closure Methodology Quick Reference Guide
2. RTL Analysis and Optimization Techniques x
2.1. Optimization Before Synthesis 2.2. Optimization After Analysis & Elaboration 2.3. Analysis After Synthesis
2.2. Optimization After Analysis & Elaboration x
2.2.1. Check Design Rules with Design Assistant 2.2.2. Preview the Design in RTL Analyzer
2.3. Analysis After Synthesis x
2.3.1. Reduce Excessive Logic Levels 2.3.2. Evaluate SDC-on-RTL Constraints 2.3.3. Verify Memory Resources 2.3.4. Confirm State Machine Recognition
3. Post-Fit Analysis and Optimization Techniques x
3.1. Define Post-Fit Timing Constraints 3.2. Analyze Post-Fit Timing Analysis Results
3.2. Analyze Post-Fit Timing Analysis Results x
3.2.1. Analyze Post-Fit Timing Reports 3.2.2. Cross-Probe with Design Assistant 3.2.3. Analyze Fitter Reports 3.2.4. Reduce Register-to-Register Delays
3.2.3. Analyze Fitter Reports x
3.2.3.1. Review RAM and DSP Reports 3.2.3.2. View Resource Usage and Congestion Reports
3.2.4. Reduce Register-to-Register Delays x
3.2.4.1. Report Logic Depth 3.2.4.2. Manually Duplicate Logic 3.2.4.3. Optimize Shift Registers
4. Additional Optimization Techniques x
4.1. Use the Fast Forward Compilation Flow 4.2. Apply Compiler Optimization Settings 4.3. Optimize the Design Floorplan 4.4. Run Design Space Explorer II 4.5. Run Exploration Dashboard 4.6. Back-Annotate Assignments
4.1. Use the Fast Forward Compilation Flow x
4.1.1. Facilitate Register Movement
Answers to Top FAQs
1. About This Application Note
2. RTL Analysis and Optimization Techniques
3. Post-Fit Analysis and Optimization Techniques
4. Additional Optimization Techniques
5. Iterative Analysis and Optimization
6. Document Revision History of AN 1016: Timing Closure Methodology Quick Reference Guide

4.2. Apply Compiler Optimization Settings

You can apply additional optimization techniques through Compiler settings and assignments. These settings and assignments can help guide the Fitter to meet your specific design requirements more effectively.

Compiler Optimization Mode Settings

Click Assignments > Settings > Compiler Settings to specify settings for the Optimization Mode. The following are among the available Optimization Mode settings:

  • Balanced—default setting that applies a balanced implementation between optimization and compile time, and is suitable for many designs.
  • High-performance effort—when performance is critical, enables extra timing optimizations during the Fitter stage, allowing the Compiler to test various settings combinations that could potentially enhance the design's speed and efficiency.
  • Superior Performance—applies an even more extensive range of timing optimizations beyond High-performance effort during synthesis. This intensive optimization enables the Fitter to explore a broader array of settings permutations, pushing for the highest performance outcome.
    Note: Note the potential trade-offs, such as increased logic area and longer compile times, which can be particularly pronounced for designs with high resource utilization.
Figure 26. Compiler Settings Dialog Box, Optimization Mode Tab


Fractal Synthesis Optimizations

You can apply fractal synthesis optimizations, tailored explicitly to benefit deep-learning accelerators and other high-throughput, arithmetic-intensive designs that exceed available DSP resources. These optimizations include multiple regularizations and retiming, resulting in a notable 20-45% area reduction for applicable designs.

I/O Assignment Optimization

You can enable individual registers within the I/O cells by using the Assignment Editor. With accurate assignments, the Fitter can appropriately place the I/O registers in the correct I/O cell or within the core to satisfy timing requirements. Additionally, you can cautiously consider programmable delays through the Assignment Editor post-compilation. These options are activated and managed by the Quartus Prime software to meet requirements. However, you can assign them to supported nodes specifically.

PLL Optimization

PLLs offer a means to adjust the phase of I/O timing on specific devices. Shifting the clock backward enhances hold time at the expense of setup time. Shifting the clock forward improves setup time at the cost of hold time. An alternative way to enhance clock skew is by using clock distribution networks. Depending on the selected device, various clock distribution networks offer optimal clock delay and skew for logic within a single quadrant. Fast regional clocks typically exhibit less delay to I/O elements than regional and global clocks, making them suitable for high fan-out control signals. Placing clocks on these low-skew, low-delay clock nets can significantly enhance performance.

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