AN 1016: Timing Closure Methodology Quick Reference Guide

Download PDF
ID 836192
Date 11/15/2024
Public

Visible to Intel only — GUID: uui1729115862867

Ixiasoft

View Details

Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. About This Application Note 2. RTL Analysis and Optimization Techniques 3. Post-Fit Analysis and Optimization Techniques 4. Additional Optimization Techniques 5. Iterative Analysis and Optimization 6. Document Revision History of AN 1016: Timing Closure Methodology Quick Reference Guide
2. RTL Analysis and Optimization Techniques x
2.1. Optimization Before Synthesis 2.2. Optimization After Analysis & Elaboration 2.3. Analysis After Synthesis
2.2. Optimization After Analysis & Elaboration x
2.2.1. Check Design Rules with Design Assistant 2.2.2. Preview the Design in RTL Analyzer
2.3. Analysis After Synthesis x
2.3.1. Reduce Excessive Logic Levels 2.3.2. Evaluate SDC-on-RTL Constraints 2.3.3. Verify Memory Resources 2.3.4. Confirm State Machine Recognition
3. Post-Fit Analysis and Optimization Techniques x
3.1. Define Post-Fit Timing Constraints 3.2. Analyze Post-Fit Timing Analysis Results
3.2. Analyze Post-Fit Timing Analysis Results x
3.2.1. Analyze Post-Fit Timing Reports 3.2.2. Cross-Probe with Design Assistant 3.2.3. Analyze Fitter Reports 3.2.4. Reduce Register-to-Register Delays
3.2.3. Analyze Fitter Reports x
3.2.3.1. Review RAM and DSP Reports 3.2.3.2. View Resource Usage and Congestion Reports
3.2.4. Reduce Register-to-Register Delays x
3.2.4.1. Report Logic Depth 3.2.4.2. Manually Duplicate Logic 3.2.4.3. Optimize Shift Registers
4. Additional Optimization Techniques x
4.1. Use the Fast Forward Compilation Flow 4.2. Apply Compiler Optimization Settings 4.3. Optimize the Design Floorplan 4.4. Run Design Space Explorer II 4.5. Run Exploration Dashboard 4.6. Back-Annotate Assignments
4.1. Use the Fast Forward Compilation Flow x
4.1.1. Facilitate Register Movement
Answers to Top FAQs
1. About This Application Note
2. RTL Analysis and Optimization Techniques
3. Post-Fit Analysis and Optimization Techniques
4. Additional Optimization Techniques
5. Iterative Analysis and Optimization
6. Document Revision History of AN 1016: Timing Closure Methodology Quick Reference Guide

3.2.4.2. Manually Duplicate Logic

Signals with high fan-out counts can cause resource congestion, complicating timing closure. The Compiler optimizes high fan-out nets during the Fitter. However, manual duplication of logic can be advantageous in specific cases, such as nets that reach multiple hierarchies of physically distant destinations, or that serve as control signals to DSP or memory blocks from combinational logic.

To guide the Compiler in duplicating registers in a pipeline chain and distributing them across hierarchies, you can specify the following assignment in the Quartus Settings File (.qsf): 

set_instance_assignment -name duplicate_hierarchy_depth -to \
   <register_name> <level_number>

This assignment creates a tree of registers following the last register of a pipelining chain, and spreads them across hierarchies. By duplicating and pushing registers down into hierarchies, the design retains the same number of cycles to all destinations while improving performance on these paths.

The following diagram shows the impact of the following example assignment:

set_instance_assignment -name duplicate_hierarchy_depth -to regZ 3
Figure 21. Impact of Assignment


Additionally, you can manually duplicate a specific register in your design using the Manual Logic Duplication option in the Assignment Editor or using the duplicate_register assignment in the .qsf as follows: 

set_instance_assignment -name duplicate_register -to 
<register_name> <num_duplicates>

This assignment allows you to specify the number of duplicates needed to alleviate the fan-out load on a register. For enhanced effectiveness, create a tree structure over multistage pipeline chains with the duplicate_register assignment. Ensure that duplicated registers are protected with a preserve attribute to prevent merging during synthesis.

The following diagram shows the impact of the following example assignment:

set_instance_assignment -name duplicate_register -to regZ 50
Figure 22. Impact of Assignment


You can track both automatic and manual duplications by reviewing the Hierarchical Tree Duplication Summary report in the Synthesis folder of the Compilation Report and the Fitter Duplication Summary available in the Place Stage folder in the Fitter stage of the Compilation Report.

Level Two Title