AN 1016: Timing Closure Methodology Quick Reference Guide

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ID 836192
Date 11/15/2024
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. About This Application Note 2. RTL Analysis and Optimization Techniques 3. Post-Fit Analysis and Optimization Techniques 4. Additional Optimization Techniques 5. Iterative Analysis and Optimization 6. Document Revision History of AN 1016: Timing Closure Methodology Quick Reference Guide
2. RTL Analysis and Optimization Techniques x
2.1. Optimization Before Synthesis 2.2. Optimization After Analysis & Elaboration 2.3. Analysis After Synthesis
2.2. Optimization After Analysis & Elaboration x
2.2.1. Check Design Rules with Design Assistant 2.2.2. Preview the Design in RTL Analyzer
2.3. Analysis After Synthesis x
2.3.1. Reduce Excessive Logic Levels 2.3.2. Evaluate SDC-on-RTL Constraints 2.3.3. Verify Memory Resources 2.3.4. Confirm State Machine Recognition
3. Post-Fit Analysis and Optimization Techniques x
3.1. Define Post-Fit Timing Constraints 3.2. Analyze Post-Fit Timing Analysis Results
3.2. Analyze Post-Fit Timing Analysis Results x
3.2.1. Analyze Post-Fit Timing Reports 3.2.2. Cross-Probe with Design Assistant 3.2.3. Analyze Fitter Reports 3.2.4. Reduce Register-to-Register Delays
3.2.3. Analyze Fitter Reports x
3.2.3.1. Review RAM and DSP Reports 3.2.3.2. View Resource Usage and Congestion Reports
3.2.4. Reduce Register-to-Register Delays x
3.2.4.1. Report Logic Depth 3.2.4.2. Manually Duplicate Logic 3.2.4.3. Optimize Shift Registers
4. Additional Optimization Techniques x
4.1. Use the Fast Forward Compilation Flow 4.2. Apply Compiler Optimization Settings 4.3. Optimize the Design Floorplan 4.4. Run Design Space Explorer II 4.5. Run Exploration Dashboard 4.6. Back-Annotate Assignments
4.1. Use the Fast Forward Compilation Flow x
4.1.1. Facilitate Register Movement
Answers to Top FAQs
1. About This Application Note
2. RTL Analysis and Optimization Techniques
3. Post-Fit Analysis and Optimization Techniques
4. Additional Optimization Techniques
5. Iterative Analysis and Optimization
6. Document Revision History of AN 1016: Timing Closure Methodology Quick Reference Guide

3.2.3.1. Review RAM and DSP Reports

If the critical path involves memory or DSP functions, it is essential to ensure that the Fitter places these functions in high-performance dedicated blocks, rather than in general-purpose logic areas. The Fitter RAM Summary and Physical RAM Information reports provide detailed information about each memory block in your design, including type, structure, implementation details, location, and additional settings. These reports are available under the Place Stage folder within the Fitter section of the Compilation Report.

Figure 13. Fitter RAM Summary Report


Additionally, the Fixed Point DSP Register Packing Details report, also available under the Plan Stage folder within the Fitter section, offers a comprehensive overview of each DSP block the design uses, detailing the DSP block's configuration and features.

Figure 14. Fixed Point DSP Register Packing Details Report


Proper definition and placement of memory blocks and DSP logic is important for the overall timing closure process. When the Fitter places these blocks in dedicated high-performance areas of the chip, rather than general-purpose logic areas, this placement helps to avoid unnecessary congestion caused by high logic utilization. This strategic placement reduces delays and interferences from long paths between logic blocks and memory or DSP blocks. Additionally, utilizing high-performance memory and DSP blocks can significantly enhance the speed and efficiency of the design.

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