AN 1016: Timing Closure Methodology Quick Reference Guide

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ID 836192
Date 11/15/2024
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. About This Application Note 2. RTL Analysis and Optimization Techniques 3. Post-Fit Analysis and Optimization Techniques 4. Additional Optimization Techniques 5. Iterative Analysis and Optimization 6. Document Revision History of AN 1016: Timing Closure Methodology Quick Reference Guide
2. RTL Analysis and Optimization Techniques x
2.1. Optimization Before Synthesis 2.2. Optimization After Analysis & Elaboration 2.3. Analysis After Synthesis
2.2. Optimization After Analysis & Elaboration x
2.2.1. Check Design Rules with Design Assistant 2.2.2. Preview the Design in RTL Analyzer
2.3. Analysis After Synthesis x
2.3.1. Reduce Excessive Logic Levels 2.3.2. Evaluate SDC-on-RTL Constraints 2.3.3. Verify Memory Resources 2.3.4. Confirm State Machine Recognition
3. Post-Fit Analysis and Optimization Techniques x
3.1. Define Post-Fit Timing Constraints 3.2. Analyze Post-Fit Timing Analysis Results
3.2. Analyze Post-Fit Timing Analysis Results x
3.2.1. Analyze Post-Fit Timing Reports 3.2.2. Cross-Probe with Design Assistant 3.2.3. Analyze Fitter Reports 3.2.4. Reduce Register-to-Register Delays
3.2.3. Analyze Fitter Reports x
3.2.3.1. Review RAM and DSP Reports 3.2.3.2. View Resource Usage and Congestion Reports
3.2.4. Reduce Register-to-Register Delays x
3.2.4.1. Report Logic Depth 3.2.4.2. Manually Duplicate Logic 3.2.4.3. Optimize Shift Registers
4. Additional Optimization Techniques x
4.1. Use the Fast Forward Compilation Flow 4.2. Apply Compiler Optimization Settings 4.3. Optimize the Design Floorplan 4.4. Run Design Space Explorer II 4.5. Run Exploration Dashboard 4.6. Back-Annotate Assignments
4.1. Use the Fast Forward Compilation Flow x
4.1.1. Facilitate Register Movement
Answers to Top FAQs
1. About This Application Note
2. RTL Analysis and Optimization Techniques
3. Post-Fit Analysis and Optimization Techniques
4. Additional Optimization Techniques
5. Iterative Analysis and Optimization
6. Document Revision History of AN 1016: Timing Closure Methodology Quick Reference Guide

2.1. Optimization Before Synthesis

The Quartus® Prime Compiler is the software component that synthesizes, places, and routes your design before generating device programming files. The Compiler is modular, allowing you to run only the stage of compilation that you need. Each Compiler stage performs a specific function in the full compilation process. The sequential modules of the Compiler include IP Generation, Analysis & Elaboration, Analysis & Synthesis, Fitter, Timing Analyzer, and Assembler.

Before running the Fitter, it is essential to identify the modules in your design that are most likely to encounter timing closure issues. These issues can arise due to multiple factors, such as complexity, clock-to-clock relationships, synchronous and asynchronous transfers, logic depth, clock skew, excessive fan-outs, or other properties. To address these potential problems effectively, start by optimizing the RTL code of these specific modules. This approach is more efficient than attempting to optimize the entire design, or by adjusting Compiler settings.

In optimizing RTL, follow these guidelines to simplify the specification of timing constraints and enhance overall performance:

  • Adhere to synchronous design techniques and a consistent coding style so that synthesis tools effectively interpret and optimize your design. Synchronous design techniques, such as ensuring a clock signal triggers all events, allow the Compiler to perform the best optimizations, resulting in accurate timing analysis results.
  • Use pipeline registers to break down large amounts of combinational logic between registers, improving speed and reducing critical path delays.
  • Avoid latch inferences and combinational loops that can cause metastability.
  • Use flipflops or RAM blocks for data storage to maintain a predictable timing behavior.
  • Ensure constructs have equivalent hardware implementations to avoid underutilizing available resources. For example, ensure that memory or DSP instantiation templates or primitives are mapped correctly to the available RAM or DSP blocks in the device.
  • Simplify cascaded conditional statements and small LUTs (Look-Up Tables) to reduce logic depth and improve timing.
  • Use Altera IP cores to represent logic in your design, wherever possible.

By following these guidelines, you can create RTL code that the Compiler can efficiently optimize, ensuring better performance and more accurate timing analysis. For more information about recommended design practices for FPGA designs, refer to Quartus Prime Pro Edition User Guide: Design Recommendations.

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