AN 1016: Timing Closure Methodology Quick Reference Guide

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ID 836192
Date 11/15/2024
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. About This Application Note 2. RTL Analysis and Optimization Techniques 3. Post-Fit Analysis and Optimization Techniques 4. Additional Optimization Techniques 5. Iterative Analysis and Optimization 6. Document Revision History of AN 1016: Timing Closure Methodology Quick Reference Guide
2. RTL Analysis and Optimization Techniques x
2.1. Optimization Before Synthesis 2.2. Optimization After Analysis & Elaboration 2.3. Analysis After Synthesis
2.2. Optimization After Analysis & Elaboration x
2.2.1. Check Design Rules with Design Assistant 2.2.2. Preview the Design in RTL Analyzer
2.3. Analysis After Synthesis x
2.3.1. Reduce Excessive Logic Levels 2.3.2. Evaluate SDC-on-RTL Constraints 2.3.3. Verify Memory Resources 2.3.4. Confirm State Machine Recognition
3. Post-Fit Analysis and Optimization Techniques x
3.1. Define Post-Fit Timing Constraints 3.2. Analyze Post-Fit Timing Analysis Results
3.2. Analyze Post-Fit Timing Analysis Results x
3.2.1. Analyze Post-Fit Timing Reports 3.2.2. Cross-Probe with Design Assistant 3.2.3. Analyze Fitter Reports 3.2.4. Reduce Register-to-Register Delays
3.2.3. Analyze Fitter Reports x
3.2.3.1. Review RAM and DSP Reports 3.2.3.2. View Resource Usage and Congestion Reports
3.2.4. Reduce Register-to-Register Delays x
3.2.4.1. Report Logic Depth 3.2.4.2. Manually Duplicate Logic 3.2.4.3. Optimize Shift Registers
4. Additional Optimization Techniques x
4.1. Use the Fast Forward Compilation Flow 4.2. Apply Compiler Optimization Settings 4.3. Optimize the Design Floorplan 4.4. Run Design Space Explorer II 4.5. Run Exploration Dashboard 4.6. Back-Annotate Assignments
4.1. Use the Fast Forward Compilation Flow x
4.1.1. Facilitate Register Movement
Answers to Top FAQs
1. About This Application Note
2. RTL Analysis and Optimization Techniques
3. Post-Fit Analysis and Optimization Techniques
4. Additional Optimization Techniques
5. Iterative Analysis and Optimization
6. Document Revision History of AN 1016: Timing Closure Methodology Quick Reference Guide

4.3. Optimize the Design Floorplan

Floorplanning is an additional technique for optimizing your design by determining the best placement of specific groups of elements within the device's physical resource. Floorplanning allows for the strategic positioning of crucial design logic to take advantage of the most beneficial locations on the chip.

While the Compiler typically automates logic placement based on various factors, such as design characteristics, settings, and constraints, Floorplanning offers a more manual approach. With Logic Lock regions, you can define custom areas within the FPGA and assign specific design nodes and properties to these regions. Utilizing the Chip Planner's visualization tools, you can easily manage the placement and properties of Logic Lock regions, enhancing your control over the physical layout of your design.

Figure 27. Chip Planner with Logic Lock Regions defined


When you specify Logic Lock regions, the Fitter gives priority to their placement and routing, which can lead to more predictable performance with each design iteration. This method is particularly effective for addressing timing issues within IP blocks that have strict timing requirements. By constraining these IP to specific areas of the chip, you can meet the necessary specifications more easily.

Floorplanning also allows the assignment of specific locations for various modules within your design. However, it is important to avoid overusing Logic Lock regions, as this can lead to inefficiencies in area usage and potential delays, especially if you place modules too distantly from one another.

For detailed guidance on optimizing your design's layout through floorplanning, the Analyzing and Optimizing the Design Floorplan section in Quartus Prime Pro Edition User Guide: Design Optimization offers insights into making the most of floorplanning to achieve a design that balances performance with efficiency.

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