AN 1016: Timing Closure Methodology Quick Reference Guide
3.2. Analyze Post-Fit Timing Analysis Results
After defining appropriate timing constraints for the design, the Fitter arranges the logic to meet or exceed these constraints. Meticulous planning and precise constraint definition can significantly reduce the number of lengthy timing closure iterations required. However, be aware that achieving optimal device performance may still require some Fitter and timing closure iterations during the physical design phase.
The Timing Analyzer detects timing requirement violations by calculating the propagation delay along each path, and analyzing the design's timing performance against your specified constraints. This analysis includes detecting critical timing issues, such as setup and hold violations, clock domain crossing problems, excessive clock skew, and propagation delays. Identifying and resolving these issues is essential to ensuring the design operates correctly and reliably within your defined timing parameters. This section describes Quartus Prime software tools for analyzing and addressing post-fit timing analysis data.