AN 1016: Timing Closure Methodology Quick Reference Guide

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ID 836192
Date 11/15/2024
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. About This Application Note 2. RTL Analysis and Optimization Techniques 3. Post-Fit Analysis and Optimization Techniques 4. Additional Optimization Techniques 5. Iterative Analysis and Optimization 6. Document Revision History of AN 1016: Timing Closure Methodology Quick Reference Guide
2. RTL Analysis and Optimization Techniques x
2.1. Optimization Before Synthesis 2.2. Optimization After Analysis & Elaboration 2.3. Analysis After Synthesis
2.2. Optimization After Analysis & Elaboration x
2.2.1. Check Design Rules with Design Assistant 2.2.2. Preview the Design in RTL Analyzer
2.3. Analysis After Synthesis x
2.3.1. Reduce Excessive Logic Levels 2.3.2. Evaluate SDC-on-RTL Constraints 2.3.3. Verify Memory Resources 2.3.4. Confirm State Machine Recognition
3. Post-Fit Analysis and Optimization Techniques x
3.1. Define Post-Fit Timing Constraints 3.2. Analyze Post-Fit Timing Analysis Results
3.2. Analyze Post-Fit Timing Analysis Results x
3.2.1. Analyze Post-Fit Timing Reports 3.2.2. Cross-Probe with Design Assistant 3.2.3. Analyze Fitter Reports 3.2.4. Reduce Register-to-Register Delays
3.2.3. Analyze Fitter Reports x
3.2.3.1. Review RAM and DSP Reports 3.2.3.2. View Resource Usage and Congestion Reports
3.2.4. Reduce Register-to-Register Delays x
3.2.4.1. Report Logic Depth 3.2.4.2. Manually Duplicate Logic 3.2.4.3. Optimize Shift Registers
4. Additional Optimization Techniques x
4.1. Use the Fast Forward Compilation Flow 4.2. Apply Compiler Optimization Settings 4.3. Optimize the Design Floorplan 4.4. Run Design Space Explorer II 4.5. Run Exploration Dashboard 4.6. Back-Annotate Assignments
4.1. Use the Fast Forward Compilation Flow x
4.1.1. Facilitate Register Movement
Answers to Top FAQs
1. About This Application Note
2. RTL Analysis and Optimization Techniques
3. Post-Fit Analysis and Optimization Techniques
4. Additional Optimization Techniques
5. Iterative Analysis and Optimization
6. Document Revision History of AN 1016: Timing Closure Methodology Quick Reference Guide

2.3.1. Reduce Excessive Logic Levels

Excessive logic levels in combinational logic can significantly impact path delay, potentially leading to critical timing issues within the design. Visualizing the number of logic levels between registers can be challenging when examining the RTL alone. However, you can use the Timing Analyzer's design metric reports to easily view the logic depths per clock domain.

To view the logic depths per clock domain, follow these steps after running Analysis & Synthesis:

  1. On the Compilation Dashboard, click the Timing Analysis icon next to the Analysis & Synthesis stage. The Timing Analyzer opens.
  2. Click Tasks > Reports > Design Metrics > Report Logic Depth.

    The Summary of Paths tab shows the Logic Depth of each path. The Data Path tab report shows all interconnected elements. The Statistics tab report summarizes the total cells and interconnect delays.

Address any logic level depth issues in these reports identify by recoding your RTL using any of the following techniques:

  • Parallelizing logic operations.
  • Pushing logic across register boundaries.
  • Use register pipelining to divide logic across multiple cycles.
    Note: You must consider the possible latency introduced in other design modules when using pipelining.
  • Flatten cascaded conditional statements and small cascaded LUTs by merging them into fewer blocks to reduce logic levels, thereby improving timing.
Figure 3. Report Logic Depth Report


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