Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813663
Date 4/01/2024
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Document Table of Contents
Document Table of Contents x
1. Low Latency Ethernet 10G MAC Intel® FPGA IP Overview 2. Getting Started 3. Functional Description 4. Parameter Settings for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core 5. Interface Signals 6. Configuration Registers 7. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
1. Low Latency Ethernet 10G MAC Intel® FPGA IP Overview x
1.1. Features 1.2. Release Information 1.3. Low Latency Ethernet 10G MAC Operating Modes 1.4. Device Family Support 1.5. Performance and Resource Utilization
1.5. Performance and Resource Utilization x
1.5.1. Resource Utilization 1.5.2. TX and RX Latency
2. Getting Started x
2.1. Introduction to Intel® FPGA IP Cores 2.2. Installing and Licensing Intel® FPGA IP Cores 2.3. Specifying the IP Core Parameters and Options ( Quartus® Prime Pro Edition) 2.4. Generated File Structure 2.5. Simulating Intel® FPGA IP Cores 2.6. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core 2.7. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Examples
2.6. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core x
2.6.1. Design Considerations
2.6.1. Design Considerations x
2.6.1.1. Timing Constraints
2.6.1.1. Timing Constraints x
2.6.1.1.1. Pseudo-Static CSR Fields 2.6.1.1.2. Clock Crosser 2.6.1.1.3. Dual Clock FIFO
2.7. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Examples x
2.7.1. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example for Agilex™ 5 Devices
3. Functional Description x
3.1. Architecture 3.2. Interfaces 3.3. Frame Types 3.4. TX Datapath 3.5. RX Datapath 3.6. Flow Control 3.7. Reset Requirements 3.8. XGMII Error Handling (Link Fault) 3.9. IEEE 1588v2
3.4. TX Datapath x
3.4.1. Padding Bytes Insertion 3.4.2. Address Insertion 3.4.3. CRC-32 Insertion 3.4.4. XGMII Encapsulation 3.4.5. Inter-Packet Gap Generation and Insertion 3.4.6. XGMII Transmission 3.4.7. TX Promiscuous (Transparent) Mode 3.4.8. TX Timing Diagrams
3.5. RX Datapath x
3.5.1. XGMII Decapsulation 3.5.2. CRC Checking 3.5.3. Address Checking 3.5.4. Frame Type Checking 3.5.5. Length Checking 3.5.6. CRC and Padding Bytes Removal 3.5.7. Overflow Handling 3.5.8. RX Promiscuous (Transparent) Mode 3.5.9. RX Timing Diagrams
3.5.5. Length Checking x
3.5.5.1. Frame Length 3.5.5.2. Payload Length
3.6. Flow Control x
3.6.1. IEEE 802.3 Flow Control 3.6.2. Priority-Based Flow Control
3.6.1. IEEE 802.3 Flow Control x
3.6.1.1. Pause Frame Reception 3.6.1.2. Pause Frame Transmission
3.6.2. Priority-Based Flow Control x
3.6.2.1. PFC Frame Reception 3.6.2.2. PFC Frame Transmission
3.9. IEEE 1588v2 x
3.9.1. Architecture 3.9.2. TX Datapath 3.9.3. RX Datapath 3.9.4. Frame Format
3.9.4. Frame Format x
3.9.4.1. PTP Packet in IEEE 802.3 3.9.4.2. PTP Packet over UDP/IPv4 3.9.4.3. PTP Packet over UDP/IPv6
5. Interface Signals x
5.1. Clock and Reset Signals 5.2. Speed Selection Signal 5.3. Error Correction Signals 5.4. Avalon® Memory-Mapped Interface Programming Signals 5.5. Avalon® Streaming Data Interfaces 5.6. Avalon® Streaming Flow Control Signals 5.7. Avalon® Streaming Status Interface 5.8. PHY-side Interfaces 5.9. IEEE 1588v2 Interfaces
5.5. Avalon® Streaming Data Interfaces x
5.5.1. Avalon® Streaming TX Data Interface Signals 5.5.2. Avalon® Streaming RX Data Interface Signals 5.5.3. Avalon® Streaming Data Interface Clocks
5.7. Avalon® Streaming Status Interface x
5.7.1. Avalon® Streaming Interface TX Status Signals 5.7.2. Avalon® Streaming Interface RX Status Signals
5.8. PHY-side Interfaces x
5.8.1. XGMII TX Signals 5.8.2. XGMII RX Signals 5.8.3. GMII TX Signals 5.8.4. GMII RX Signals 5.8.5. Clock Enable Signals
5.9. IEEE 1588v2 Interfaces x
5.9.1. IEEE 1588v2 Egress TX Signals 5.9.2. IEEE 1588v2 Ingress RX Signals 5.9.3. IEEE 1588v2 Interface Clocks
6. Configuration Registers x
6.1. Register Map 6.2. Register Access Definition 6.3. Primary MAC Address 6.4. MAC Reset Control Register 6.5. TX Configuration and Status Registers 6.6. Flow Control Registers 6.7. RX Configuration and Status Registers 6.8. ECC Registers 6.9. Statistics Registers 6.10. Timestamp Registers
6.10. Timestamp Registers x
6.10.1. Calculating PHY Total Latency 6.10.2. Calculating Deterministic Latency 6.10.3. PTP Register Configuration
1. Low Latency Ethernet 10G MAC Intel® FPGA IP Overview
2. Getting Started
3. Functional Description
4. Parameter Settings for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
5. Interface Signals
6. Configuration Registers
7. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

6.5. TX Configuration and Status Registers

Table 36.  TX Configuration and Status Registers
Word Offset Register Name Description Access HW Reset Value
0x0020 tx_packet_control
  • Bit 0—configures the TX path.

    0: Enables the TX path.

    1: Disables the TX path. The MAC IP core indicates a backpressure on the Avalon® streaming transmit data interface by deasserting the avalon_st_tx_ready signal. When disabled, the IP core stops generating new pause and PFC frames.

  • Bits 31:1—reserved.

You can change the value of this register as necessary. If the TX path is disabled while a frame is being transmitted, the MAC IP core completes the transmission before disabling the TX path.

RW 0x0
0x0022 tx_transfer_status

The MAC sets the following bits to indicate the status of the TX datapath.

  • Bits 7:0—reserved.
  • Bit 8: TX datapath status.

    0: The TX datapath is idle.

    1: A TX data transfer is in progress.

  • Bits 11:9—reserved.
  • Bit 12: TX datapath reset status.

    0: The TX datapath is not in reset.

    1: The TX datapath is in reset.

 RO 0x0
0x0024 tx_pad_control
  • Bit 0—padding insertion enable on transmit.

    0: Disables padding insertion. The client must ensure that the length of the data frame meets the minimum length as required by the IEEE 802.3 specifications.

    1: Enables padding insertion. The MAC IP core inserts padding bytes into the data frames from the client to meet the minimum length as required by the IEEE 802.3 specifications.

    When padding insertion is enabled, you must set tx_crc_control[] to 0x3 to enable CRC insertion.

  • Bits 31:1—reserved.

Configure this register before you enable the MAC IP core for operations.

RW 0x1
0x0026 tx_crc_control
  • Bit 0—always set this bit to 1.
  • Bit 1—configures CRC insertion.

    0: Disables CRC insertion. The client must provide the CRC field and ensure that the length of the data frame meets the minimum required length.

    1: Enables CRC insertion. The MAC IP core computes the CRC field and inserts it into the data frame.

  • Bits 31:2—reserved.

Configure this register before you enable the MAC IP core for operations.

RW 0x3
0x0028 tx_preamble_control 3
  • Bit 0—always set this bit to 1.
  • Bit 1—configures CRC insertion.

    0: Disables CRC insertion. The client must provide the CRC field and ensure that the length of the data frame meets the minimum required length.

    1: Enables CRC insertion. The MAC IP core computes the CRC field and inserts it into the data frame.

  • Bits 31:2—reserved.

Configure this register before you enable the MAC IP core for operations.

RW

0x3
0x002A tx_src_addr_override
  • Bit 0—configures source address override.

    0: Disables source address override. The client must fill the source address field with a valid address..

    1: Enables source address override. The MAC IP core overwrites the source address field in data frames with the primary MAC address specified in the tx_primary_mac_addr0 and tx_primary_mac_addr1 registers.

  • Bits 31:1—reserved.

Configure this register before you enable the MAC IP core for operations.

RW 0x0
0x002C tx_frame_maxlength
  • Bits 15:0—specify the maximum allowable frame length. The MAC IP core uses this register only for the purpose of collecting statistics. When the length of the data frame from the client exceeds this value, the MAC IP core asserts the avalon_st_txstatus_error[1] signal to flag the frame as oversized. The MAC IP core then forwards the oversized frame through the transmit datapath as is.
  • Bits 31:16—reserved.

Configure this register before you enable the MAC IP core for operations.

RW 0x5EE (1518)
0x002D tx_vlan_detection
  • Bit 0—TX VLAN detection disable.

    0: The MAC detects VLAN and stacked VLAN frames.

    1: The MAC does not detect VLAN and stacked VLAN frames. When received, the MAC treats them as basic frames and considers their tags as payload bytes.

  • Bits 31:1—reserved.
 RW 0x0

0x002E

0x081E

 tx_ipg_10g
  • Bit 0—use this bit to specify the average IPG for operating speed of 10 Gbps.

    0: Sets the average IPG to 8 bytes.

    1: Sets the average IPG to 12 bytes.

  • Bits 31:1—reserved.

The Unidirectional feature does not support an average IPG of 8 bytes.

If you turn on Use legacy Ethernet 10G MAC Avalon® memory-mapped interface , the word offset is 0x081E. Otherwise, the word offset is 0x002E.

RW 0x1

0x002F

0x081F

 tx_ipg_10M_100M_1G
  • Bits 3:0—use these bits to specify the average IPG for operating speed of 10 Mbps, 100 Mbps or 1 Gbps. Valid values are between 8 to 15 bytes.
  • Bits 31:4—reserved.

If you turn on Use legacy Ethernet 10G MAC Avalon® memory-mapped interface , the word offset is 0x081F. Otherwise, the word offset is 0x002F.

RW 0x0C
0x003E tx_underflow_counter0

36-bit error counter that collects the number of truncated TX frames when TX buffer underflow persists.

  • tx_underflow_counter0: Lower 32 bits of the error counter.
  • tx_underflow_counter1[3:0]: Upper 4 bits of the error counter.
  • tx_underflow_counter1[31:4]—reserved.

To read the counter, read the lower 32 bits followed by the upper 4 bits. The IP core clears the counter after a read.

 RO 0x0
0x003F tx_underflow_counter1
3 This register is used only when you turn on Enable preamble pass-through mode option. It is reserved when not used.
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