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1. Low Latency Ethernet 10G MAC Intel® FPGA IP Overview
2. Getting Started
3. Functional Description
4. Parameter Settings for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
5. Interface Signals
6. Configuration Registers
7. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
2.1. Introduction to Intel® FPGA IP Cores
2.2. Installing and Licensing Intel® FPGA IP Cores
2.3. Specifying the IP Core Parameters and Options ( Quartus® Prime Pro Edition)
2.4. Generated File Structure
2.5. Simulating Intel® FPGA IP Cores
2.6. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
2.7. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Examples
5.1. Clock and Reset Signals
5.2. Speed Selection Signal
5.3. Error Correction Signals
5.4. Avalon® Memory-Mapped Interface Programming Signals
5.5. Avalon® Streaming Data Interfaces
5.6. Avalon® Streaming Flow Control Signals
5.7. Avalon® Streaming Status Interface
5.8. PHY-side Interfaces
5.9. IEEE 1588v2 Interfaces
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3.5.8. RX Promiscuous (Transparent) Mode
In receive path promiscuous mode, a valid received packet is not checked whether it is intended for this MAC, that is the "Destination Address" field of the packet is not compared against the pre-programmed primary MAC address and supplementary addresses (if this feature is enabled).
This can be achieved by setting various register fields to:
- Enable acceptance of all received unicast frames
- Enable acceptance of all multicast frames
A packet with broadcast address is always accepted by the MAC.
Under the RX promiscuous mode, the START, PREAMBLE, SFD, EFD, and IDLE characters are always stripped off by the MAC during decapsulation process.