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1. Low Latency Ethernet 10G MAC Intel® FPGA IP Overview
2. Getting Started
3. Functional Description
4. Parameter Settings for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
5. Interface Signals
6. Configuration Registers
7. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
2.1. Introduction to Intel® FPGA IP Cores
2.2. Installing and Licensing Intel® FPGA IP Cores
2.3. Specifying the IP Core Parameters and Options ( Quartus® Prime Pro Edition)
2.4. Generated File Structure
2.5. Simulating Intel® FPGA IP Cores
2.6. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
2.7. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Examples
5.1. Clock and Reset Signals
5.2. Speed Selection Signal
5.3. Error Correction Signals
5.4. Avalon® Memory-Mapped Interface Programming Signals
5.5. Avalon® Streaming Data Interfaces
5.6. Avalon® Streaming Flow Control Signals
5.7. Avalon® Streaming Status Interface
5.8. PHY-side Interfaces
5.9. IEEE 1588v2 Interfaces
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5.9.2. IEEE 1588v2 Ingress RX Signals
The signals below are present when you select the Enable time stamping option.
Signal | Direction | Width | Description |
---|---|---|---|
rx_ingress_timestamp_96b_valid | Out | 1 | When asserted, this signal checks for a valid timestamp on rx_ingress_timestamp_96b_data[]. The MAC IP core asserts this signal in the same clock cycle it asserts avalon_st_rx_startofpacket. |
rx_ingress_timestamp_96b_data[] | Out | 96 | Carries the 96-bit ingress timestamp in the following format:
|
rx_ingress_timestamp_64b_valid | Out | 1 | When asserted, this signal checks for a valid timestamp on rx_ingress_timestamp_64b_data[]. The MAC IP core asserts this signal in the same clock cycle it asserts avalon_st_rx_startofpacket. |
rx_ingress_timestamp_64b_data[] | Out | 64 | Carries the 64-bit ingress timestamp in the following format:
|
rx_time_of_day_96b_10g_data rx_time_of_day_96b_1g_data |
In | 96 | Carries the time-of-day (TOD) from an external TOD module to the MAC IP core in the following format:
|
rx_time_of_day_64b_10g_data rx_time_of_day_96b_1g_data |
In | 64 | Carries the TOD from an external TOD module the MAC IP core in the following format:
|
rx_path_delay_10g_data[15:0] | In | 16 | Connect this bus to the PHY Intel® FPGA IP. This bus carries the path delay (residence time), measured between the physical network and the PHY side of the MAC IP Core (XGMII, GMII, or MII). The MAC IP core uses this value when generating the ingress timestamp to account for the delay. The path delay is in the following format:
|
rx_path_delay_10g_data[23:0] (for USXGMII speed mode) | In | 24 | |
rx_path_delay_1g_data[21:0] |
In | 22 | Connect this bus to the PHY Intel® FPGA IP. This bus carries the path delay, which is measured between the physical network and the PHY side of the MAC IP Core (GMII or MII). The MAC IP core uses this value when generating the ingress timestamp to account for the delay. The path delay is in the following format:
|
rx_ingress_p2p_val[] | Out | 46 | Represents <meanPathDelay> for the current ingress port, which is used for peer-to-peer operations.
|
rx_ingress_p2p_val_valid | Out | 1 | When asserted, this signal indicates the rx_ingress_p2p_val is valid. |