Visible to Intel only — GUID: bhc1395127805671
Ixiasoft
Visible to Intel only — GUID: bhc1395127805671
Ixiasoft
5.7.2. Avalon® Streaming Interface RX Status Signals
Signal | Direction | Width | Description |
---|---|---|---|
avalon_st_rxstatus_valid | Out | 1 | When asserted, this signal qualifies the avalon_st_rxstatus_data[] and avalon_st_rxstatus_error[] signals. The MAC IP core asserts this signal in the same clock cycle the avalon_st_rx_endofpacket signal is asserted. |
avalon_st_rxstatus_data[] | Out | 40 | Contains information about the RX frame.
|
avalon_st_rxstatus_error[] | Out | 7 | When set to 1, the respective bit indicates the following error type in the RX frame.
The IP core presents the error status on this bus in the same clock cycle it asserts the avalon_st_rxstatus_valid signal. The error status is invalid when an overflow occurs. |
avalon_st_rx_pfc_status_valid | Out | 1 | When asserted, this signal qualifies the avalon_st_rx_pfc_status_data[] signal. This signal applies only to 10G operating mode. |
avalon_st_rx_pfc_status_data[] | Out | n (4 - 16) |
n = 2 x Number of PFC queues parameter When set to 1, the respective bit indicates the flow control request from the remote partner, for example:
When a pair of bits (Example: Bit 0 and Bit 1, Bit 3 and Bit 4, etc.) is set to 0, the respective bit indicates there is no flow control frame sent. This signal applies only to 10G operating mode. |