Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813663
Date 4/01/2024
Public

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2.4. Generated File Structure

The Quartus® Prime Pro Edition software generates the following IP core output file structure.
Figure 5. Generated IP Files
Table 7.  Generated IP Files

File Name

Description

<your_ip>.ip

The Platform Designer system or top-level IP variation file. <your_ip> is the name that you give your IP variation.

<your_ip>.cmp The VHDL Component Declaration (.cmp) file. It is a text file that contains local generic and port definitions that you can use in VHDL design files.

This IP core does not support VHDL. However, the Quartus® Prime Pro Edition software generates this file.

<your_ip>_generation.rpt IP or Platform Designer generation log file. A summary of the messages during IP generation.
<your_ip>.qgsimc Lists simulation parameters to support incremental regeneration.
<your_ip>.qgsynthc Lists synthesis parameters to support incremental regeneration.
<your_ip>.qip

Contains all the required information about the IP component to integrate and compile the IP component in the Quartus® Prime software.

<your_ip>.csv Contains information about the upgrade status of the IP component.

<your_ip>.bsf

A Block Symbol File (.bsf) representation of the IP variation for use in Quartus® Prime Block Diagram Files (.bdf).

<your_ip>.spd

Required input file for ip-make-simscript to generate simulation scripts for supported simulators. The .spd file contains a list of files generated for simulation, along with information about memories that you can initialize.

<your_ip>.ppf The Pin Planner File (.ppf) stores the port and node assignments for IP components created for use with the Pin Planner.
<your_ip>_bb.v You can use the Verilog black-box (_bb.v) file as an empty module declaration for use as a black box.
<your_ip>_inst.v or _inst.vhd HDL example instantiation template. You can copy and paste the contents of this file into your HDL file to instantiate the IP variation.

This IP core does not support VHDL. However, the Quartus® Prime Pro Edition software generates the _inst.vhd file.

<your_ip>.regmap If the IP contains register information, the Quartus® Prime software generates the .regmap file. The .regmap file describes the register map information of host and agent interfaces. This file complements the .sopcinfo file by providing more detailed register information about the system. This file enables register display views and user customizable statistics in System Console.
<your_ip>.svd

Allows HPS System Debug tools to view the register maps of peripherals that connect to the HPS within a Platform Designer system.

During synthesis, the Quartus® Prime software stores the .svd files for agent interface that is visible to the System Console hosts in the .sof file in the debug session. System Console reads this section, which Platform Designer query for register map information. For system agents, Platform Designer can access the registers by name.

<your_ip>.v

<your_ip>.vhd

HDL files that instantiate each submodule or child IP core for synthesis or simulation.
mentor/

Contains a ModelSim* script msim_setup.tcl to set up and run a simulation.

synopsys/vcs/

synopsys/vcsmx/

Contains a shell script vcs_setup.sh to set up and run a VCS* simulation.

Contains a shell script vcsmx_setup.sh and synopsys_ sim.setup file to set up and run a VCS MX* simulation.

/xcelium Contains an Xcelium* Parallel simulator shell script xcelium_setup.sh and other setup files to set up and run a simulation.
submodules/ Contains HDL files for the IP core submodules.
<child IP cores>/ For each generated child IP core directory, Platform Designer generates synth/ and sim/ sub-directories.